addere.map.rpt

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path     ;
+----------------------------------+-----------------+------------------------------------+----------------------------------+
; AdderE.vqm                       ; yes             ; User Verilog Quartus Mapping File  ; E:/QProj/AdderE/rev_1/AdderE.vqm ;
+----------------------------------+-----------------+------------------------------------+----------------------------------+


+---------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                               ;
+---------------------------------+-----------------------------------------+
; Resource                        ; Usage                                   ;
+---------------------------------+-----------------------------------------+
; Total logic elements            ; 16                                      ;
; Total combinational functions   ; 16                                      ;
;     -- Total 4-input functions  ; 0                                       ;
;     -- Total 3-input functions  ; 16                                      ;
;     -- Total 2-input functions  ; 0                                       ;
;     -- Total 1-input functions  ; 0                                       ;
;     -- Total 0-input functions  ; 0                                       ;
; Combinational cells for routing ; 0                                       ;
; Total registers                 ; 0                                       ;
; I/O pins                        ; 26                                      ;
; Maximum fan-out node            ; Full_Adder_1:Stages_6_OtherBits_FA|COUT ;
; Maximum fan-out                 ; 2                                       ;
; Total fan-out                   ; 57                                      ;
; Average fan-out                 ; 1.36                                    ;
+---------------------------------+-----------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                           ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------+
; Compilation Hierarchy Node              ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                        ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------+
; |AdderE                                 ; 16 (0)      ; 0            ; 0           ; 26   ; 0            ; 16 (0)       ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE                                    ;
;    |Full_Adder:Stages_0_LowBit_FA|      ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder:Stages_0_LowBit_FA      ;
;    |Full_Adder_1:Stages_6_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_1:Stages_6_OtherBits_FA ;
;    |Full_Adder_2:Stages_1_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_2:Stages_1_OtherBits_FA ;
;    |Full_Adder_3:Stages_7_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_3:Stages_7_OtherBits_FA ;
;    |Full_Adder_4:Stages_5_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_4:Stages_5_OtherBits_FA ;
;    |Full_Adder_5:Stages_2_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_5:Stages_2_OtherBits_FA ;
;    |Full_Adder_6:Stages_3_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_6:Stages_3_OtherBits_FA ;
;    |Full_Adder_7:Stages_4_OtherBits_FA| ; 2 (2)       ; 0            ; 0           ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |AdderE|Full_Adder_7:Stages_4_OtherBits_FA ;
+-----------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+--------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/QProj/AdderE/rev_1/AdderE.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu May 04 16:42:26 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off AdderE -c AdderE
Info: Found 9 design units, including 9 entities, in source file AdderE.vqm
    Info: Found entity 1: Full_Adder
    Info: Found entity 2: Full_Adder_1
    Info: Found entity 3: Full_Adder_2
    Info: Found entity 4: Full_Adder_3
    Info: Found entity 5: Full_Adder_4
    Info: Found entity 6: Full_Adder_5
    Info: Found entity 7: Full_Adder_6
    Info: Found entity 8: Full_Adder_7
    Info: Found entity 9: AdderE
Info: Elaborating entity "AdderE" for the top level hierarchy
Info: Elaborating entity "Full_Adder" for hierarchy "Full_Adder:Stages_0_LowBit_FA"
Info: Elaborating entity "Full_Adder_1" for hierarchy "Full_Adder_1:Stages_6_OtherBits_FA"
Info: Elaborating entity "Full_Adder_2" for hierarchy "Full_Adder_2:Stages_1_OtherBits_FA"
Info: Elaborating entity "Full_Adder_3" for hierarchy "Full_Adder_3:Stages_7_OtherBits_FA"
Info: Elaborating entity "Full_Adder_4" for hierarchy "Full_Adder_4:Stages_5_OtherBits_FA"
Info: Elaborating entity "Full_Adder_5" for hierarchy "Full_Adder_5:Stages_2_OtherBits_FA"
Info: Elaborating entity "Full_Adder_6" for hierarchy "Full_Adder_6:Stages_3_OtherBits_FA"
Info: Elaborating entity "Full_Adder_7" for hierarchy "Full_Adder_7:Stages_4_OtherBits_FA"
Info: Implemented 42 device resources after synthesis - the final resource count might be different
    Info: Implemented 17 input pins
    Info: Implemented 9 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Processing ended: Thu May 04 16:42:32 2006
    Info: Elapsed time: 00:00:08