📄 addere.srr
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$ Start of Compile
#Thu May 04 11:26:56 2006
Synplicity VHDL Compiler, version Compilers 2.8.1, Build 050R, built Oct 6 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Synthesizing work.addere.syn
Synthesizing work.full_adder.syn
Post processing for work.full_adder.syn
Post processing for work.addere.syn
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Altera Technology Mapper, version 7.7.0, Build 054R, built Oct 6 2004
Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved
@N: MT210 |Because the design is Purely Combinational, Autoconstrain mode is TURNED OFF
@N: MF197 |Retiming summary : 0 registers retimed to 0
##### BEGIN RETIMING REPORT #####
Retiming summary : 0 registers retimed to 0
Original and Pipelined registers replaced by retiming :
None
New registers created by retiming :
None
##### END RETIMING REPORT #####
Writing Analyst data base E:\QProj\AdderE\rev_1\AdderE.srm
Writing Verilog Netlist and constraint files
Writing .vqm output for Quartus
Writing Cross reference file for Quartus to E:\QProj\AdderE\rev_1\AdderE.xrf
##### START OF TIMING REPORT #####[
# Timing Report written on Thu May 04 11:26:58 2006
#
Top view: AdderE
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 5
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..
Performance Summary
*******************
Worst slack in design: 985.309
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
------------------------------------------------------------------------------------------------------------------
System 1.0 MHz 68.1 MHz 1000.000 14.691 985.309 system default_clkgroup
==================================================================================================================
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
----------------------------------------------------------------------------
A[0] System (rising) NA 0.000 985.309 985.309
A[1] System (rising) NA 0.000 986.215 986.215
A[2] System (rising) NA 0.000 987.121 987.121
A[3] System (rising) NA 0.000 988.027 988.027
A[4] System (rising) NA 0.000 988.933 988.933
A[5] System (rising) NA 0.000 989.839 989.839
A[6] System (rising) NA 0.000 990.745 990.745
A[7] System (rising) NA 0.000 991.651 991.651
B[0] System (rising) NA 0.000 985.457 985.457
B[1] System (rising) NA 0.000 986.363 986.363
B[2] System (rising) NA 0.000 987.269 987.269
B[3] System (rising) NA 0.000 988.175 988.175
B[4] System (rising) NA 0.000 989.081 989.081
B[5] System (rising) NA 0.000 989.987 989.987
B[6] System (rising) NA 0.000 990.893 990.893
B[7] System (rising) NA 0.000 991.799 991.799
CIN System (rising) NA 0.000 985.607 985.607
============================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------
COUT System (rising) NA 14.691 1000.000 985.309
SUM[0] System (rising) NA 8.349 1000.000 991.651
SUM[1] System (rising) NA 9.255 1000.000 990.745
SUM[2] System (rising) NA 10.161 1000.000 989.839
SUM[3] System (rising) NA 11.067 1000.000 988.933
SUM[4] System (rising) NA 11.973 1000.000 988.027
SUM[5] System (rising) NA 12.879 1000.000 987.121
SUM[6] System (rising) NA 13.785 1000.000 986.215
SUM[7] System (rising) NA 14.691 1000.000 985.309
==============================================================================
====================================
Detailed Report for Clock: System
====================================
Starting Points with Worst Slack
********************************
Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------
A[7:0] System Port A[0] A[0] 0.000 985.309
B[7:0] System Port B[0] B[0] 0.000 985.457
CIN System Port CIN CIN 0.000 985.607
A[7:0] System Port A[1] A[1] 0.000 986.215
B[7:0] System Port B[1] B[1] 0.000 986.363
A[7:0] System Port A[2] A[2] 0.000 987.121
B[7:0] System Port B[2] B[2] 0.000 987.269
A[7:0] System Port A[3] A[3] 0.000 988.027
B[7:0] System Port B[3] B[3] 0.000 988.175
A[7:0] System Port A[4] A[4] 0.000 988.933
=========================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
------------------------------------------------------------------------------
COUT System Port COUT COUT 1000.000 985.309
SUM[7:0] System Port SUM[7] SUM[7] 1000.000 985.309
SUM[7:0] System Port SUM[6] SUM[6] 1000.000 986.215
SUM[7:0] System Port SUM[5] SUM[5] 1000.000 987.121
SUM[7:0] System Port SUM[4] SUM[4] 1000.000 988.027
SUM[7:0] System Port SUM[3] SUM[3] 1000.000 988.933
SUM[7:0] System Port SUM[2] SUM[2] 1000.000 989.839
SUM[7:0] System Port SUM[1] SUM[1] 1000.000 990.745
SUM[7:0] System Port SUM[0] SUM[0] 1000.000 991.651
==============================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 1000.000
= Required time: 1000.000
- Propagation time: 14.691
= Slack (critical) : 985.309
Number of logic level(s): 10
Starting point: A[7:0] / A[0]
Ending point: COUT / COUT
The start point is clocked by System [rising]
The end point is clocked by System [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-----------------------------------------------------------------------------------------------------
A[7:0] Port A[0] In 0.000 0.000 -
A[0] Net - - 0.000 - 0
A_in[0] cyclone_io padio In - 0.000 -
A_in[0] cyclone_io combout Out 1.328 1.328 -
A_c[0] Net - - 1.613 - 2
Stages.0.LowBit.FA.COUT cyclone_lcell dataa In - 2.941 -
Stages.0.LowBit.FA.COUT cyclone_lcell combout Out 0.590 3.531 -
COUT Net - - 0.614 - 2
Stages.1.OtherBits.FA.COUT cyclone_lcell datac In - 4.145 -
Stages.1.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 4.437 -
COUT Net - - 0.614 - 2
Stages.2.OtherBits.FA.COUT cyclone_lcell datac In - 5.051 -
Stages.2.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 5.343 -
COUT Net - - 0.614 - 2
Stages.3.OtherBits.FA.COUT cyclone_lcell datac In - 5.957 -
Stages.3.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 6.249 -
COUT Net - - 0.614 - 2
Stages.4.OtherBits.FA.COUT cyclone_lcell datac In - 6.863 -
Stages.4.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 7.155 -
COUT Net - - 0.614 - 2
Stages.5.OtherBits.FA.COUT cyclone_lcell datac In - 7.769 -
Stages.5.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 8.061 -
COUT Net - - 0.614 - 2
Stages.6.OtherBits.FA.COUT cyclone_lcell datac In - 8.675 -
Stages.6.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 8.967 -
COUT Net - - 0.614 - 2
Stages.7.OtherBits.FA.COUT cyclone_lcell datac In - 9.581 -
Stages.7.OtherBits.FA.COUT cyclone_lcell combout Out 0.292 9.873 -
N_5_i Net - - 1.487 - 1
COUT_out cyclone_io datain In - 11.360 -
COUT_out cyclone_io padio Out 3.331 14.691 -
COUT Net - - 0.000 - 0
COUT Port COUT Out - 14.691 -
=====================================================================================================
Total path delay (propagation time + setup) of 14.691 is 7.293(49.6%) logic and 7.398(50.4%) route.
##### END OF TIMING REPORT #####]
##### START OF AREA REPORT #####[
Design view:work.AdderE(syn)
Selecting part EP1C6F256C8
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
I/O ATOMs: 26
Total LUTs: 16 of 5980 ( 0%)
Logic resources: 16 ATOMs of 5980 ( 0%)
ATOM count by mode:
normal: 16
arithmetic: 0
ShiftTap: 0 (0 registers)
Total ESB: 0 bits (0% of 81920)
ATOMs using regout pin: 0
also using enable pin: 0
also using combout pin: 0
ATOMs using combout pin: 16
Number of Inputs on ATOMs: 48
Number of Nets: 117
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]
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