ddfsdemo.hier_info

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

|DDFSDemo
DDFSOUT[0] <= DDFSCore:inst3.DDFSOUT[0]
DDFSOUT[1] <= DDFSCore:inst3.DDFSOUT[1]
DDFSOUT[2] <= DDFSCore:inst3.DDFSOUT[2]
DDFSOUT[3] <= DDFSCore:inst3.DDFSOUT[3]
DDFSOUT[4] <= DDFSCore:inst3.DDFSOUT[4]
DDFSOUT[5] <= DDFSCore:inst3.DDFSOUT[5]
DDFSOUT[6] <= DDFSCore:inst3.DDFSOUT[6]
DDFSOUT[7] <= DDFSCore:inst3.DDFSOUT[7]
CLK => PLL:inst.inclk0
LUT_WREN => DDFSCore:inst3.LUT_WREN
FREQ_WORDS[0] => DDFSCore:inst3.FREQ_WORDS[0]
FREQ_WORDS[1] => DDFSCore:inst3.FREQ_WORDS[1]
FREQ_WORDS[2] => DDFSCore:inst3.FREQ_WORDS[2]
FREQ_WORDS[3] => DDFSCore:inst3.FREQ_WORDS[3]
FREQ_WORDS[4] => DDFSCore:inst3.FREQ_WORDS[4]
FREQ_WORDS[5] => DDFSCore:inst3.FREQ_WORDS[5]
FREQ_WORDS[6] => DDFSCore:inst3.FREQ_WORDS[6]
FREQ_WORDS[7] => DDFSCore:inst3.FREQ_WORDS[7]
FREQ_WORDS[8] => DDFSCore:inst3.FREQ_WORDS[8]
FREQ_WORDS[9] => DDFSCore:inst3.FREQ_WORDS[9]
FREQ_WORDS[10] => DDFSCore:inst3.FREQ_WORDS[10]
FREQ_WORDS[11] => DDFSCore:inst3.FREQ_WORDS[11]
FREQ_WORDS[12] => DDFSCore:inst3.FREQ_WORDS[12]
FREQ_WORDS[13] => DDFSCore:inst3.FREQ_WORDS[13]
FREQ_WORDS[14] => DDFSCore:inst3.FREQ_WORDS[14]
FREQ_WORDS[15] => DDFSCore:inst3.FREQ_WORDS[15]
FREQ_WORDS[16] => DDFSCore:inst3.FREQ_WORDS[16]
FREQ_WORDS[17] => DDFSCore:inst3.FREQ_WORDS[17]
FREQ_WORDS[18] => DDFSCore:inst3.FREQ_WORDS[18]
FREQ_WORDS[19] => DDFSCore:inst3.FREQ_WORDS[19]
LUT_ADD[0] => DDFSCore:inst3.LUT_ADD[0]
LUT_ADD[1] => DDFSCore:inst3.LUT_ADD[1]
LUT_ADD[2] => DDFSCore:inst3.LUT_ADD[2]
LUT_ADD[3] => DDFSCore:inst3.LUT_ADD[3]
LUT_ADD[4] => DDFSCore:inst3.LUT_ADD[4]
LUT_ADD[5] => DDFSCore:inst3.LUT_ADD[5]
LUT_ADD[6] => DDFSCore:inst3.LUT_ADD[6]
LUT_ADD[7] => DDFSCore:inst3.LUT_ADD[7]
LUT_ADD[8] => DDFSCore:inst3.LUT_ADD[8]
LUT_ADD[9] => DDFSCore:inst3.LUT_ADD[9]
LUT_DATA[0] => DDFSCore:inst3.LUT_DATA[0]
LUT_DATA[1] => DDFSCore:inst3.LUT_DATA[1]
LUT_DATA[2] => DDFSCore:inst3.LUT_DATA[2]
LUT_DATA[3] => DDFSCore:inst3.LUT_DATA[3]
LUT_DATA[4] => DDFSCore:inst3.LUT_DATA[4]
LUT_DATA[5] => DDFSCore:inst3.LUT_DATA[5]
LUT_DATA[6] => DDFSCore:inst3.LUT_DATA[6]
LUT_DATA[7] => DDFSCore:inst3.LUT_DATA[7]
PHASE_WORDS[0] => DDFSCore:inst3.PHASE_WORDS[0]
PHASE_WORDS[1] => DDFSCore:inst3.PHASE_WORDS[1]
PHASE_WORDS[2] => DDFSCore:inst3.PHASE_WORDS[2]
PHASE_WORDS[3] => DDFSCore:inst3.PHASE_WORDS[3]
PHASE_WORDS[4] => DDFSCore:inst3.PHASE_WORDS[4]
PHASE_WORDS[5] => DDFSCore:inst3.PHASE_WORDS[5]
PHASE_WORDS[6] => DDFSCore:inst3.PHASE_WORDS[6]
PHASE_WORDS[7] => DDFSCore:inst3.PHASE_WORDS[7]
PHASE_WORDS[8] => DDFSCore:inst3.PHASE_WORDS[8]
PHASE_WORDS[9] => DDFSCore:inst3.PHASE_WORDS[9]


|DDFSDemo|DDFSCore:inst3
CLK => reg_G_FreqWords[18].CLK
CLK => reg_G_FreqWords[17].CLK
CLK => reg_G_FreqWords[16].CLK
CLK => reg_G_FreqWords[15].CLK
CLK => reg_G_FreqWords[14].CLK
CLK => reg_G_FreqWords[13].CLK
CLK => reg_G_FreqWords[12].CLK
CLK => reg_G_FreqWords[11].CLK
CLK => reg_G_FreqWords[10].CLK
CLK => reg_G_FreqWords[9].CLK
CLK => reg_G_FreqWords[8].CLK
CLK => reg_G_FreqWords[7].CLK
CLK => reg_G_FreqWords[6].CLK
CLK => reg_G_FreqWords[5].CLK
CLK => reg_G_FreqWords[4].CLK
CLK => reg_G_FreqWords[3].CLK
CLK => reg_G_FreqWords[2].CLK
CLK => reg_G_FreqWords[1].CLK
CLK => reg_G_FreqWords[0].CLK
CLK => reg_G_PhaseWords[9].CLK
CLK => reg_G_PhaseWords[8].CLK
CLK => reg_G_PhaseWords[7].CLK
CLK => reg_G_PhaseWords[6].CLK
CLK => reg_G_PhaseWords[5].CLK
CLK => reg_G_PhaseWords[4].CLK
CLK => reg_G_PhaseWords[3].CLK
CLK => reg_G_PhaseWords[2].CLK
CLK => reg_G_PhaseWords[1].CLK
CLK => reg_G_PhaseWords[0].CLK
CLK => arith_G_FreqAcc[23].CLK
CLK => arith_G_FreqAcc[22].CLK
CLK => arith_G_FreqAcc[21].CLK
CLK => arith_G_FreqAcc[20].CLK
CLK => arith_G_FreqAcc[19].CLK
CLK => arith_G_FreqAcc[18].CLK
CLK => arith_G_FreqAcc[17].CLK
CLK => arith_G_FreqAcc[16].CLK
CLK => arith_G_FreqAcc[15].CLK
CLK => arith_G_FreqAcc[14].CLK
CLK => arith_G_FreqAcc[13].CLK
CLK => arith_G_FreqAcc[12].CLK
CLK => arith_G_FreqAcc[11].CLK
CLK => arith_G_FreqAcc[10].CLK
CLK => arith_G_FreqAcc[9].CLK
CLK => arith_G_FreqAcc[8].CLK
CLK => arith_G_FreqAcc[7].CLK
CLK => arith_G_FreqAcc[6].CLK
CLK => arith_G_FreqAcc[5].CLK
CLK => arith_G_FreqAcc[4].CLK
CLK => arith_G_FreqAcc[3].CLK
CLK => arith_G_FreqAcc[2].CLK
CLK => arith_G_FreqAcc[1].CLK
CLK => arith_G_FreqAcc[0].CLK
CLK => altsyncram:altsyncram_component.clock0
CLK => reg_G_FreqWords[19].CLK
DDFSOUT[0] <= altsyncram:altsyncram_component.q_b[0]
DDFSOUT[1] <= altsyncram:altsyncram_component.q_b[1]
DDFSOUT[2] <= altsyncram:altsyncram_component.q_b[2]
DDFSOUT[3] <= altsyncram:altsyncram_component.q_b[3]
DDFSOUT[4] <= altsyncram:altsyncram_component.q_b[4]
DDFSOUT[5] <= altsyncram:altsyncram_component.q_b[5]
DDFSOUT[6] <= altsyncram:altsyncram_component.q_b[6]
DDFSOUT[7] <= altsyncram:altsyncram_component.q_b[7]
LUT_DATA[0] => altsyncram:altsyncram_component.data_a[0]
LUT_DATA[1] => altsyncram:altsyncram_component.data_a[1]
LUT_DATA[2] => altsyncram:altsyncram_component.data_a[2]
LUT_DATA[3] => altsyncram:altsyncram_component.data_a[3]
LUT_DATA[4] => altsyncram:altsyncram_component.data_a[4]
LUT_DATA[5] => altsyncram:altsyncram_component.data_a[5]
LUT_DATA[6] => altsyncram:altsyncram_component.data_a[6]
LUT_DATA[7] => altsyncram:altsyncram_component.data_a[7]
LUT_ADD[0] => altsyncram:altsyncram_component.address_a[0]
LUT_ADD[1] => altsyncram:altsyncram_component.address_a[1]
LUT_ADD[2] => altsyncram:altsyncram_component.address_a[2]
LUT_ADD[3] => altsyncram:altsyncram_component.address_a[3]
LUT_ADD[4] => altsyncram:altsyncram_component.address_a[4]
LUT_ADD[5] => altsyncram:altsyncram_component.address_a[5]
LUT_ADD[6] => altsyncram:altsyncram_component.address_a[6]
LUT_ADD[7] => altsyncram:altsyncram_component.address_a[7]
LUT_ADD[8] => altsyncram:altsyncram_component.address_a[8]
LUT_ADD[9] => altsyncram:altsyncram_component.address_a[9]
LUT_WREN => altsyncram:altsyncram_component.wren_a
FREQ_WORDS[0] => reg_G_FreqWords[0].DATAIN
FREQ_WORDS[1] => reg_G_FreqWords[1].DATAIN
FREQ_WORDS[2] => reg_G_FreqWords[2].DATAIN
FREQ_WORDS[3] => reg_G_FreqWords[3].DATAIN
FREQ_WORDS[4] => reg_G_FreqWords[4].DATAIN
FREQ_WORDS[5] => reg_G_FreqWords[5].DATAIN
FREQ_WORDS[6] => reg_G_FreqWords[6].DATAIN
FREQ_WORDS[7] => reg_G_FreqWords[7].DATAIN
FREQ_WORDS[8] => reg_G_FreqWords[8].DATAIN
FREQ_WORDS[9] => reg_G_FreqWords[9].DATAIN
FREQ_WORDS[10] => reg_G_FreqWords[10].DATAIN
FREQ_WORDS[11] => reg_G_FreqWords[11].DATAIN
FREQ_WORDS[12] => reg_G_FreqWords[12].DATAIN
FREQ_WORDS[13] => reg_G_FreqWords[13].DATAIN
FREQ_WORDS[14] => reg_G_FreqWords[14].DATAIN
FREQ_WORDS[15] => reg_G_FreqWords[15].DATAIN
FREQ_WORDS[16] => reg_G_FreqWords[16].DATAIN
FREQ_WORDS[17] => reg_G_FreqWords[17].DATAIN
FREQ_WORDS[18] => reg_G_FreqWords[18].DATAIN
FREQ_WORDS[19] => reg_G_FreqWords[19].DATAIN
PHASE_WORDS[0] => reg_G_PhaseWords[0].DATAIN
PHASE_WORDS[1] => reg_G_PhaseWords[1].DATAIN
PHASE_WORDS[2] => reg_G_PhaseWords[2].DATAIN
PHASE_WORDS[3] => reg_G_PhaseWords[3].DATAIN
PHASE_WORDS[4] => reg_G_PhaseWords[4].DATAIN
PHASE_WORDS[5] => reg_G_PhaseWords[5].DATAIN
PHASE_WORDS[6] => reg_G_PhaseWords[6].DATAIN
PHASE_WORDS[7] => reg_G_PhaseWords[7].DATAIN
PHASE_WORDS[8] => reg_G_PhaseWords[8].DATAIN
PHASE_WORDS[9] => reg_G_PhaseWords[9].DATAIN


|DDFSDemo|DDFSCore:inst3|altsyncram:altsyncram_component
wren_a => altsyncram_tme1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_tme1:auto_generated.data_a[0]
data_a[1] => altsyncram_tme1:auto_generated.data_a[1]
data_a[2] => altsyncram_tme1:auto_generated.data_a[2]
data_a[3] => altsyncram_tme1:auto_generated.data_a[3]
data_a[4] => altsyncram_tme1:auto_generated.data_a[4]
data_a[5] => altsyncram_tme1:auto_generated.data_a[5]
data_a[6] => altsyncram_tme1:auto_generated.data_a[6]
data_a[7] => altsyncram_tme1:auto_generated.data_a[7]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
data_b[5] => ~NO_FANOUT~
data_b[6] => ~NO_FANOUT~
data_b[7] => ~NO_FANOUT~
address_a[0] => altsyncram_tme1:auto_generated.address_a[0]
address_a[1] => altsyncram_tme1:auto_generated.address_a[1]
address_a[2] => altsyncram_tme1:auto_generated.address_a[2]
address_a[3] => altsyncram_tme1:auto_generated.address_a[3]
address_a[4] => altsyncram_tme1:auto_generated.address_a[4]
address_a[5] => altsyncram_tme1:auto_generated.address_a[5]
address_a[6] => altsyncram_tme1:auto_generated.address_a[6]
address_a[7] => altsyncram_tme1:auto_generated.address_a[7]
address_a[8] => altsyncram_tme1:auto_generated.address_a[8]
address_a[9] => altsyncram_tme1:auto_generated.address_a[9]
address_b[0] => altsyncram_tme1:auto_generated.address_b[0]
address_b[1] => altsyncram_tme1:auto_generated.address_b[1]
address_b[2] => altsyncram_tme1:auto_generated.address_b[2]
address_b[3] => altsyncram_tme1:auto_generated.address_b[3]
address_b[4] => altsyncram_tme1:auto_generated.address_b[4]
address_b[5] => altsyncram_tme1:auto_generated.address_b[5]
address_b[6] => altsyncram_tme1:auto_generated.address_b[6]
address_b[7] => altsyncram_tme1:auto_generated.address_b[7]
address_b[8] => altsyncram_tme1:auto_generated.address_b[8]
address_b[9] => altsyncram_tme1:auto_generated.address_b[9]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_tme1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_a[5] <= <GND>
q_a[6] <= <GND>
q_a[7] <= <GND>
q_b[0] <= altsyncram_tme1:auto_generated.q_b[0]
q_b[1] <= altsyncram_tme1:auto_generated.q_b[1]
q_b[2] <= altsyncram_tme1:auto_generated.q_b[2]
q_b[3] <= altsyncram_tme1:auto_generated.q_b[3]
q_b[4] <= altsyncram_tme1:auto_generated.q_b[4]
q_b[5] <= altsyncram_tme1:auto_generated.q_b[5]
q_b[6] <= altsyncram_tme1:auto_generated.q_b[6]
q_b[7] <= altsyncram_tme1:auto_generated.q_b[7]


|DDFSDemo|DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR