ddfsdemo.fit.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "49 unused 3.30 49 0 0 " "Info: Number of I/O pins in group: 49 (unused VREF, 3.30 VCCIO, 49 input, 0 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use unused 3 41 " "Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used --  41 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 48 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 8 37 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  37 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 48 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  48 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.367 ns memory pin " "Info: Estimated most critical path is memory to pin delay of 9.367 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~portb_address_reg0 1 MEM M4K_X17_Y6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~portb_address_reg0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~portb_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 236 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|q_b\[6\] 2 MEM M4K_X17_Y6 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y6; Fanout = 1; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|q_b\[6\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.317 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~portb_address_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[6] } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 40 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.926 ns) + CELL(2.124 ns) 9.367 ns DDFSOUT\[6\] 3 PIN PIN_N15 0 " "Info: 3: + IC(2.926 ns) + CELL(2.124 ns) = 9.367 ns; Loc. = PIN_N15; Fanout = 0; PIN Node = 'DDFSOUT\[6\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "5.050 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[6] DDFSOUT[6] } "NODE_NAME" } "" } } { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -736 288 464 -720 "DDFSOUT\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.441 ns 68.76 % " "Info: Total cell delay = 6.441 ns ( 68.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.926 ns 31.24 % " "Info: Total interconnect delay = 2.926 ns ( 31.24 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "9.367 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~portb_address_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[6] DDFSOUT[6] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}