ddfsdemo.fit.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources." {  } {  } 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "PLL:inst\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"PLL:inst\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "PLL:inst\|altpll:altpll_component\|_clk0" } { 0 "PLL:inst\|altpll:altpll_component\|_clk0" } } } } { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -720 -296 -56 -560 "inst" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "D:/QProj/DDFSDemo/DDFSDemo.fld" "" { Floorplan "D:/QProj/DDFSDemo/DDFSDemo.fld" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}