ddfsdemo.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "CLK pin FREQ_WORDS\[10\] register DDFSCore:inst3\|reg_G_FreqWords\[10\] 3.361 ns " "Info: Minimum slack time is 3.361 ns for clock \"CLK\" between source pin \"FREQ_WORDS\[10\]\" and destination register \"DDFSCore:inst3\|reg_G_FreqWords\[10\]\"" { { "Info" "ITDB_FULL_TH_REQUIREMENT" "1.000 ns + register " "Info: + th requirement for source pin and destination register is 1.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TH_RESULT" "-2.361 ns - " "Info: - th from clock to input pin is -2.361 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK PLL:inst\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -768 -296 -128 -752 "CLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 destination 2.353 ns + Longest register " "Info: + Longest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns DDFSCore:inst3\|reg_G_FreqWords\[10\] 2 REG LC_X25_Y1_N8 3 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X25_Y1_N8; Fanout = 3; REG Node = 'DDFSCore:inst3\|reg_G_FreqWords\[10\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 79 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 30.22 % " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.78 % " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 79 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.844 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.844 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns FREQ_WORDS\[10\] 1 PIN PIN_P11 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_P11; Fanout = 1; PIN Node = 'FREQ_WORDS\[10\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { FREQ_WORDS[10] } "NODE_NAME" } "" } } { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -488 -288 -88 -472 "FREQ_WORDS\[19..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(0.115 ns) 2.844 ns DDFSCore:inst3\|reg_G_FreqWords\[10\] 2 REG LC_X25_Y1_N8 3 " "Info: 2: + IC(1.254 ns) + CELL(0.115 ns) = 2.844 ns; Loc. = LC_X25_Y1_N8; Fanout = 3; REG Node = 'DDFSCore:inst3\|reg_G_FreqWords\[10\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "1.369 ns" { FREQ_WORDS[10] DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 79 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 55.91 % " "Info: Total cell delay = 1.590 ns ( 55.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.254 ns 44.09 % " "Info: Total interconnect delay = 1.254 ns ( 44.09 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.844 ns" { FREQ_WORDS[10] DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.844 ns" { FREQ_WORDS[10] FREQ_WORDS[10]~out0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 0.0ns 1.254ns } { 0.0ns 1.475ns 0.115ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.844 ns" { FREQ_WORDS[10] DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.844 ns" { FREQ_WORDS[10] FREQ_WORDS[10]~out0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 0.0ns 1.254ns } { 0.0ns 1.475ns 0.115ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.844 ns" { FREQ_WORDS[10] DDFSCore:inst3|reg_G_FreqWords[10] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.844 ns" { FREQ_WORDS[10] FREQ_WORDS[10]~out0 DDFSCore:inst3|reg_G_FreqWords[10] } { 0.0ns 0.0ns 1.254ns } { 0.0ns 1.475ns 0.115ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Jun 10 15:31:42 2006 " "Info: Processing ended: Sat Jun 10 15:31:42 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}