ddfsdemo.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK " "Info: No valid register-to-register data paths exist for clock \"CLK\"" {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 register DDFSCore:inst3\|arith_G_FreqAcc\[23\] register DDFSCore:inst3\|arith_G_FreqAcc\[23\] 1.032 ns " "Info: Minimum slack time is 1.032 ns for clock \"PLL:inst\|altpll:altpll_component\|_clk0\" between source register \"DDFSCore:inst3\|arith_G_FreqAcc\[23\]\" and destination register \"DDFSCore:inst3\|arith_G_FreqAcc\[23\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.823 ns + Shortest register register " "Info: + Shortest register to register delay is 0.823 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDFSCore:inst3\|arith_G_FreqAcc\[23\] 1 REG LC_X20_Y4_N6 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y4_N6; Fanout = 2; REG Node = 'DDFSCore:inst3\|arith_G_FreqAcc\[23\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.514 ns) + CELL(0.309 ns) 0.823 ns DDFSCore:inst3\|arith_G_FreqAcc\[23\] 2 REG LC_X20_Y4_N6 2 " "Info: 2: + IC(0.514 ns) + CELL(0.309 ns) = 0.823 ns; Loc. = LC_X20_Y4_N6; Fanout = 2; REG Node = 'DDFSCore:inst3\|arith_G_FreqAcc\[23\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "0.823 ns" { DDFSCore:inst3|arith_G_FreqAcc[23] DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 37.55 % " "Info: Total cell delay = 0.309 ns ( 37.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.514 ns 62.45 % " "Info: Total interconnect delay = 0.514 ns ( 62.45 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "0.823 ns" { DDFSCore:inst3|arith_G_FreqAcc[23] DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { DDFSCore:inst3|arith_G_FreqAcc[23] DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 0.514ns } { 0.0ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst\|altpll:altpll_component\|_clk0 6.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is 6.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst\|altpll:altpll_component\|_clk0 6.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is 6.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 destination 2.353 ns + Longest register " "Info: + Longest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to destination register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns DDFSCore:inst3\|arith_G_FreqAcc\[23\] 2 REG LC_X20_Y4_N6 2 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X20_Y4_N6; Fanout = 2; REG Node = 'DDFSCore:inst3\|arith_G_FreqAcc\[23\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 30.22 % " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.78 % " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 source 2.353 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to source register is 2.353 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.711 ns) 2.353 ns DDFSCore:inst3\|arith_G_FreqAcc\[23\] 2 REG LC_X20_Y4_N6 2 " "Info: 2: + IC(1.642 ns) + CELL(0.711 ns) = 2.353 ns; Loc. = LC_X20_Y4_N6; Fanout = 2; REG Node = 'DDFSCore:inst3\|arith_G_FreqAcc\[23\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 30.22 % " "Info: Total cell delay = 0.711 ns ( 30.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.78 % " "Info: Total interconnect delay = 1.642 ns ( 69.78 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "DDFSCore.vhd" "" { Text "D:/QProj/DDFSDemo/DDFSCore.vhd" 77 -1 0 } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "0.823 ns" { DDFSCore:inst3|arith_G_FreqAcc[23] DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.823 ns" { DDFSCore:inst3|arith_G_FreqAcc[23] DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 0.514ns } { 0.0ns 0.309ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.353 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|arith_G_FreqAcc[23] } { 0.0ns 1.642ns } { 0.0ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK pin LUT_ADD\[6\] memory DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6 3.469 ns " "Info: Slack time is 3.469 ns for clock \"CLK\" between source pin \"LUT_ADD\[6\]\" and destination memory \"DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6\"" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "8.000 ns + memory " "Info: + tsu requirement for source pin and destination memory is 8.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TSU_RESULT" "4.531 ns - " "Info: - tsu from clock to input pin is 4.531 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.917 ns + Longest pin memory " "Info: + Longest pin to memory delay is 4.917 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns LUT_ADD\[6\] 1 PIN PIN_R7 2 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_R7; Fanout = 2; PIN Node = 'LUT_ADD\[6\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { LUT_ADD[6] } "NODE_NAME" } "" } } { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -520 -256 -88 -504 "LUT_ADD\[9..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.059 ns) + CELL(0.383 ns) 4.917 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(3.059 ns) + CELL(0.383 ns) = 4.917 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "3.442 ns" { LUT_ADD[6] DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 236 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns 37.79 % " "Info: Total cell delay = 1.858 ns ( 37.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.059 ns 62.21 % " "Info: Total interconnect delay = 3.059 ns ( 62.21 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.917 ns" { LUT_ADD[6] DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.917 ns" { LUT_ADD[6] LUT_ADD[6]~out0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 0.000ns 3.059ns } { 0.000ns 1.475ns 0.383ns } } }  } 0} { "Info" "ITDB_FULL_PLL_OFFSET" "CLK PLL:inst\|altpll:altpll_component\|_clk0 -1.885 ns - " "Info: - Offset between input clock \"CLK\" and output clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -768 -296 -128 -752 "CLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 236 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 destination 2.364 ns - Shortest memory " "Info: - Shortest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to destination memory is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.722 ns) 2.364 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6 2 MEM M4K_X17_Y6 0 " "Info: 2: + IC(1.642 ns) + CELL(0.722 ns) = 2.364 ns; Loc. = M4K_X17_Y6; Fanout = 0; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a6~porta_address_reg6'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 236 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns 30.54 % " "Info: Total cell delay = 0.722 ns ( 30.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.46 % " "Info: Total interconnect delay = 1.642 ns ( 69.46 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.917 ns" { LUT_ADD[6] DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.917 ns" { LUT_ADD[6] LUT_ADD[6]~out0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 0.000ns 3.059ns } { 0.000ns 1.475ns 0.383ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.917 ns" { LUT_ADD[6] DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.917 ns" { LUT_ADD[6] LUT_ADD[6]~out0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 0.000ns 3.059ns } { 0.000ns 1.475ns 0.383ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a6~porta_address_reg6 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLK memory DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9 pin DDFSOUT\[1\] 628 ps " "Info: Slack time is 628 ps for clock \"CLK\" between source memory \"DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9\" and destination pin \"DDFSOUT\[1\]\"" { { "Info" "ITDB_FULL_TCO_REQUIREMENT" "11.000 ns + memory " "Info: + tco requirement for source memory and destination pin is 11.000 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TCO_RESULT" "10.372 ns - " "Info: - tco from clock to output pin is 10.372 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "CLK PLL:inst\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"CLK\" and output clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is -1.885 ns" {  } { { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -768 -296 -128 -752 "CLK" "" } } } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 source 2.360 ns + Longest memory " "Info: + Longest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to source memory is 2.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.718 ns) 2.360 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9 2 MEM M4K_X17_Y5 4 " "Info: 2: + IC(1.642 ns) + CELL(0.718 ns) = 2.360 ns; Loc. = M4K_X17_Y5; Fanout = 4; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.718 ns 30.42 % " "Info: Total cell delay = 0.718 ns ( 30.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.58 % " "Info: Total interconnect delay = 1.642 ns ( 69.58 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } { 0.000ns 1.642ns } { 0.000ns 0.718ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.247 ns + Longest memory pin " "Info: + Longest memory to pin delay is 9.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9 1 MEM M4K_X17_Y5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y5; Fanout = 4; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~portb_address_reg9'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.317 ns) 4.317 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|q_b\[1\] 2 MEM M4K_X17_Y5 1 " "Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X17_Y5; Fanout = 1; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|q_b\[1\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.317 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 40 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.806 ns) + CELL(2.124 ns) 9.247 ns DDFSOUT\[1\] 3 PIN PIN_L16 0 " "Info: 3: + IC(2.806 ns) + CELL(2.124 ns) = 9.247 ns; Loc. = PIN_L16; Fanout = 0; PIN Node = 'DDFSOUT\[1\]'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.930 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } "NODE_NAME" } "" } } { "DDFSDemo.bdf" "" { Schematic "D:/QProj/DDFSDemo/DDFSDemo.bdf" { { -736 288 464 -720 "DDFSOUT\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.441 ns 69.66 % " "Info: Total cell delay = 6.441 ns ( 69.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.806 ns 30.34 % " "Info: Total interconnect delay = 2.806 ns ( 30.34 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } { 0.000ns 0.000ns 2.806ns } { 0.000ns 4.317ns 2.124ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } { 0.000ns 1.642ns } { 0.000ns 0.718ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } { 0.000ns 0.000ns 2.806ns } { 0.000ns 4.317ns 2.124ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.360 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 } { 0.000ns 1.642ns } { 0.000ns 0.718ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.247 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~portb_address_reg9 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|q_b[1] DDFSOUT[1] } { 0.000ns 0.000ns 2.806ns } { 0.000ns 4.317ns 2.124ns } } }  } 0}