ddfsdemo.tan.qmsg

郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程

{ "Warning" "WTAN_PLL_CONFLICTING_GLOBAL_FMAX" "PLL:inst\|altpll:altpll_component\|_clk0 166.67 MHz 166.69 MHz " "Warning: ClockLock PLL \"PLL:inst\|altpll:altpll_component\|_clk0\" input frequency requirement of 166.67 MHz overrides default required fmax of 166.69 MHz -- Slack information will be reported" {  } {  } 0}
{ "Warning" "WTAN_IGNORE_MINIMUM_ASSIGNMENTS" "" "Warning: Ignored minimum timing requirements(s) -- minimum timing requirements analyzed only when minimum analysis is run" {  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 memory DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0 memory DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0 924 ps " "Info: Slack time is 924 ps for clock \"PLL:inst\|altpll:altpll_component\|_clk0\" between source memory \"DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0\" and destination memory \"DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "5.243 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 5.243 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "6.000 ns + " "Info: + Setup relationship between source and destination is 6.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 4.115 ns " "Info: + Latch edge is 4.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst\|altpll:altpll_component\|_clk0 6.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is 6.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst\|altpll:altpll_component\|_clk0 6.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"PLL:inst\|altpll:altpll_component\|_clk0\" is 6.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 destination 2.350 ns + Shortest memory " "Info: + Shortest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to destination memory is 2.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.708 ns) 2.350 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0 2 MEM M4K_X17_Y5 0 " "Info: 2: + IC(1.642 ns) + CELL(0.708 ns) = 2.350 ns; Loc. = M4K_X17_Y5; Fanout = 0; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns 30.13 % " "Info: Total cell delay = 0.708 ns ( 30.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.87 % " "Info: Total interconnect delay = 1.642 ns ( 69.87 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst\|altpll:altpll_component\|_clk0 source 2.364 ns - Longest memory " "Info: - Longest clock path from clock \"PLL:inst\|altpll:altpll_component\|_clk0\" to source memory is 2.364 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst\|altpll:altpll_component\|_clk0 1 CLK PLL_1 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 110; CLK Node = 'PLL:inst\|altpll:altpll_component\|_clk0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { PLL:inst|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.642 ns) + CELL(0.722 ns) 2.364 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0 2 MEM M4K_X17_Y5 1 " "Info: 2: + IC(1.642 ns) + CELL(0.722 ns) = 2.364 ns; Loc. = M4K_X17_Y5; Fanout = 1; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.722 ns 30.54 % " "Info: Total cell delay = 0.722 ns ( 30.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.642 ns 69.46 % " "Info: Total interconnect delay = 1.642 ns ( 69.46 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0 1 MEM M4K_X17_Y5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y5; Fanout = 1; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_datain_reg0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0 2 MEM M4K_X17_Y5 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X17_Y5; Fanout = 0; MEM Node = 'DDFSCore:inst3\|altsyncram:altsyncram_component\|altsyncram_tme1:auto_generated\|ram_block1a7~porta_memory_reg0'" {  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.319 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_tme1.tdf" "" { Text "D:/QProj/DDFSDemo/db/altsyncram_tme1.tdf" 268 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.319 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0}  } { { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.350 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.708ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.364 ns" { PLL:inst|altpll:altpll_component|_clk0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 } { 0.000ns 1.642ns } { 0.000ns 0.722ns } } } { "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" "" { Report "D:/QProj/DDFSDemo/db/DDFSDemo_cmp.qrpt" Compiler "DDFSDemo" "UNKNOWN" "V1" "D:/QProj/DDFSDemo/db/DDFSDemo.quartus_db" { Floorplan "D:/QProj/DDFSDemo/" "" "4.319 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.319 ns" { DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_datain_reg0 DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated|ram_block1a7~porta_memory_reg0 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0}