ddfsdemo.hif

来自「郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程」· HIF 代码 · 共 2,049 行 · 第 1/2 页

Version 5.0 Build 148 04/26/2005 SJ Full Version
32
1618
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
synplcty.lmf
# entity
PLL
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
PLL.vhd
1147922382
4
# storage
db|DDFSDemo.(1).cnf
db|DDFSDemo.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
PLL:inst
}
# end
# entity
altsyncram_qte1
# case_insensitive
# source_file
db|altsyncram_qte1.tdf
1148145896
6
# storage
db|DDFSDemo.(9).cnf
db|DDFSDemo.(9).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
q_b8
q_b9
}
# memory_file {
ddfsSINLUT.hex
1148145850
}
# end
# entity
DDFSDemo
# case_insensitive
# source_file
DDFSDemo.bdf
1149305296
23
# storage
db|DDFSDemo.(0).cnf
db|DDFSDemo.(0).cnf
# hierarchies {
|
}
# end
# entity
altsyncram_tme1
# case_insensitive
# source_file
db|altsyncram_tme1.tdf
1148952595
6
# storage
db|DDFSDemo.(4).cnf
db|DDFSDemo.(4).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
}
# memory_file {
sin_rom1024.mif
1149579250
}
# hierarchies {
DDFSCore:inst3|altsyncram:altsyncram_component|altsyncram_tme1:auto_generated
}
# end
# entity
cntr_cn8
# case_insensitive
# source_file
db|cntr_cn8.tdf
1149580965
6
# storage
db|DDFSDemo.(27).cnf
db|DDFSDemo.(27).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
}
# end
# entity
cntr_419
# case_insensitive
# source_file
db|cntr_419.tdf
1149580965
6
# storage
db|DDFSDemo.(30).cnf
db|DDFSDemo.(30).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
}
# end
# entity
cntr_1r9
# case_insensitive
# source_file
db|cntr_1r9.tdf
1149580966
6
# storage
db|DDFSDemo.(42).cnf
db|DDFSDemo.(42).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
cout
}
# end
# entity
cntr_tt7
# case_insensitive
# source_file
db|cntr_tt7.tdf
1149580967
6
# storage
db|DDFSDemo.(48).cnf
db|DDFSDemo.(48).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
}
# end
# entity
cntr_nk7
# case_insensitive
# source_file
db|cntr_nk7.tdf
1149580967
6
# storage
db|DDFSDemo.(50).cnf
db|DDFSDemo.(50).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
}
# end
# entity
decode_9ie
# case_insensitive
# source_file
db|decode_9ie.tdf
1149580968
6
# storage
db|DDFSDemo.(58).cnf
db|DDFSDemo.(58).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
cntr_po8
# case_insensitive
# source_file
db|cntr_po8.tdf
1149581158
6
# storage
db|DDFSDemo.(68).cnf
db|DDFSDemo.(68).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
cntr_h29
# case_insensitive
# source_file
db|cntr_h29.tdf
1149581158
6
# storage
db|DDFSDemo.(71).cnf
db|DDFSDemo.(71).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
cntr_7u9
# case_insensitive
# source_file
db|cntr_7u9.tdf
1149581159
6
# storage
db|DDFSDemo.(82).cnf
db|DDFSDemo.(82).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
cout
}
# end
# entity
decode_fga
# case_insensitive
# source_file
db|decode_fga.tdf
1149581160
6
# storage
db|DDFSDemo.(86).cnf
db|DDFSDemo.(86).cnf
# used_port {
data0
enable
eq0
eq1
}
# end
# entity
mux_vab
# case_insensitive
# source_file
db|mux_vab.tdf
1149581160
6
# storage
db|DDFSDemo.(87).cnf
db|DDFSDemo.(87).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
sel0
result0
result1
result2
result3
result4
result5
result6
result7
}
# end
# entity
cntr_tn7
# case_insensitive
# source_file
db|cntr_tn7.tdf
1149581160
6
# storage
db|DDFSDemo.(90).cnf
db|DDFSDemo.(90).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
q10
q11
q12
}
# end
# entity
cntr_en8
# case_insensitive
# source_file
db|cntr_en8.tdf
1149582151
6
# storage
db|DDFSDemo.(100).cnf
db|DDFSDemo.(100).cnf
# used_port {
clock
clk_en
aset
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
cntr_619
# case_insensitive
# source_file
db|cntr_619.tdf
1149582151
6
# storage
db|DDFSDemo.(103).cnf
db|DDFSDemo.(103).cnf
# used_port {
clock
clk_en
cnt_en
aclr
sclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
cntr_0r9
# case_insensitive
# source_file
db|cntr_0r9.tdf
1149582152
6
# storage
db|DDFSDemo.(112).cnf
db|DDFSDemo.(112).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
cout
}
# end
# entity
cntr_jv7
# case_insensitive
# source_file
db|cntr_jv7.tdf
1149582152
6
# storage
db|DDFSDemo.(118).cnf
db|DDFSDemo.(118).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
}
# end
# entity
cntr_mk7
# case_insensitive
# source_file
db|cntr_mk7.tdf
1149582153
6
# storage
db|DDFSDemo.(120).cnf
db|DDFSDemo.(120).cnf
# used_port {
clock
clk_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
}
# end
# entity
altsyncram
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|DDFSDemo.(3).cnf
db|DDFSDemo.(3).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_DEC
USR
WIDTHAD_A
10
PARAMETER_DEC
USR
NUMWORDS_A
1024
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_DEC
USR
WIDTHAD_B
10
PARAMETER_DEC
USR
NUMWORDS_B
1024
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK0
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
INIT_FILE
sin_rom1024.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_tme1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_b0
address_b1
address_b2
address_b3
address_b4
address_b5
address_b6
address_b7
address_b8
address_b9
clock0
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
q_b0
q_b1
q_b2
q_b3
q_b4
q_b5
q_b6
q_b7
wren_a
}
# include_file {
c:|altera|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
c:|altera|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
c:|altera|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
c:|altera|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
c:|altera|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
c:|altera|quartus50|libraries|megafunctions|aglobal50.inc
1114012420
c:|altera|quartus50|libraries|megafunctions|altdpram.inc
1107573082
c:|altera|quartus50|libraries|megafunctions|altrom.inc
1107573422
c:|altera|quartus50|libraries|megafunctions|altram.inc
1107573384
c:|altera|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
DDFSCore:inst3|altsyncram:altsyncram_component
}
# end
# entity
altpll
# case_insensitive
# source_file
c:|altera|quartus50|libraries|megafunctions|altpll.tdf
1114012436
6
# storage
db|DDFSDemo.(5).cnf
db|DDFSDemo.(5).cnf
# user_parameter {
OPERATION_MODE
NORMAL
PARAMETER_UNKNOWN
USR
PLL_TYPE
AUTO
PARAMETER_UNKNOWN
USR
QUALIFY_CONF_DONE
OFF
PARAMETER_UNKNOWN
DEF
COMPENSATE_CLOCK
CLK0
PARAMETER_UNKNOWN
USR
SCAN_CHAIN
LONG
PARAMETER_UNKNOWN
DEF
PRIMARY_CLOCK
INCLK0
PARAMETER_UNKNOWN
DEF
INCLK0_INPUT_FREQUENCY
20000
PARAMETER_DEC
USR
INCLK1_INPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
GATE_LOCK_SIGNAL
NO
PARAMETER_UNKNOWN
DEF
GATE_LOCK_COUNTER
0
PARAMETER_UNKNOWN
DEF
LOCK_HIGH
1
PARAMETER_UNKNOWN
DEF
LOCK_LOW
1
PARAMETER_UNKNOWN
DEF
VALID_LOCK_MULTIPLIER
1
PARAMETER_UNKNOWN
DEF
INVALID_LOCK_MULTIPLIER
5
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_LOSSCLK
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_ON_GATED_LOCK
OFF
PARAMETER_UNKNOWN
DEF
ENABLE_SWITCH_OVER_COUNTER
OFF
PARAMETER_UNKNOWN
DEF
SKIP_VCO
OFF
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_COUNTER
0
PARAMETER_UNKNOWN
DEF
SWITCH_OVER_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
FEEDBACK_SOURCE
EXTCLK0
PARAMETER_UNKNOWN
DEF
BANDWIDTH
0
PARAMETER_UNKNOWN
DEF
BANDWIDTH_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
SPREAD_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
DOWN_SPREAD
0
PARAMETER_UNKNOWN
DEF