📄 sdr_sdram_tb.vhd
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if (datain /= start_value + i - 1 ) then
assert false
REPORT "read data mis-match"
SEVERITY FAILURE;
end if;
end loop;
wait for 200 ns;
cmd <= "100"; -- close the bank with a precharge
wait until (cmdack = '1');
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000";
end page_read_burst;
-- config(cl, rc, bl, pm, ref)
--
-- This task cofigures the SDRAM devices and the controller
--
-- cl : Cas latency, 2 or 3
-- rc : Ras to Cas delay.
-- bl : Burst length 1,2,4, or 8
-- pm : page mode setting
-- ref : refresh period setting
procedure config ( cl: std_logic_vector(2 downto 0);
rc: std_logic_vector(1 downto 0);
bl: integer;
pm: std_logic;
ref: std_logic_vector(15 downto 0);
signal addr: out std_logic_vector(ASIZE-1 downto 0);
signal cmdack: std_logic;
signal cmd: out std_logic_vector(2 downto 0)) is
begin
addr <= (others => '0');
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "100";
wait until (cmdack = '1');
wait until (CLK'event and CLK = '1'); -- Wait for the controller to ack the command
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
if (bl = 1) then
addr(2 downto 0) <= "000"; -- Set the Burst length portion of the mode data
elsif (bl = 2) then
addr(2 downto 0) <= "001";
elsif (bl = 4) then
addr(2 downto 0) <= "010";
elsif (bl = 8) then
addr(2 downto 0) <= "011";
elsif (bl = 0) then
addr(2 downto 0) <= "111"; -- full page burst configuration value for bl
end if;
addr(6 downto 4) <= cl;
cmd <= "101";
wait until (cmdack = '1'); -- Wait for the controller to ack the command
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
wait until (CLK'event and CLK = '1');
wait until (CLK'event and CLK = '1');
wait for 1 ns;
addr(15 downto 0) <= ref;
cmd <= "111"; -- load refresh counter
wait until (cmdack = '1'); -- Wait for the controller to ack the command
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
addr(1 downto 0) <= cl(1 downto 0); -- load contorller reg1
addr(3 downto 2) <= rc;
addr(8) <= pm;
if (bl = 1) then
addr(12 downto 9) <= "0001"; -- Set the Burst length portion of the mode data
elsif (bl = 2) then
addr(12 downto 9) <= "0010";
elsif (bl = 4) then
addr(12 downto 9) <= "0100";
elsif (bl = 8) then
addr(12 downto 9) <= "1000";
elsif (bl = 0) then
addr(12 downto 9) <= "1000"; -- full page burst configuration value for bl
end if;
cmd <= "110";
wait until (cmdack = '1'); -- Wait for the controller to ack the command
wait until (CLK'event and CLK = '1');
wait for 1 ns;
cmd <= "000"; -- Clear the command by issuing a NOP
end config;
begin
-- The SDRAM Controller
sdr: sdr_sdram
port map (
CLK => clk,
RESET_N => reset_n,
ADDR => addr,
CMD => cmd,
CMDACK => cmdack,
DATAIN => datain,
DATAOUT => dataout,
DM => dm,
SA => sa,
BA => ba,
CS_N => cs_n,
CKE => cke,
RAS_N => ras_n,
CAS_N => cas_n,
WE_N => we_n,
DQ => dq,
DQM => dqm
);
-- The SDRAMs
B00: mt48lc8m16a2
port map(
Dq => dq(15 downto 0),
Addr => sa(11 downto 0),
Ba => ba,
CLK => clk2,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dqm => dqm(1 downto 0)
);
B01: mt48lc8m16a2
port map(
Dq => dq(31 downto 16),
Addr => sa(11 downto 0),
Ba => ba,
CLK => clk2,
Cke => cke,
Cs_n => cs_n(0),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dqm => dqm(3 downto 2)
);
B10: mt48lc8m16a2
port map(
Dq => dq(15 downto 0),
Addr => sa(11 downto 0),
Ba => ba,
CLK => clk2,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dqm => dqm(1 downto 0)
);
B11: mt48lc8m16a2
port map(
Dq => dq(31 downto 16),
Addr => sa(11 downto 0),
Ba => ba,
CLK => clk2,
Cke => cke,
Cs_n => cs_n(1),
Cas_n => cas_n,
Ras_n => ras_n,
We_n => we_n,
Dqm => dqm(3 downto 2)
);
-- Generate the clocks
-- clocks for 133mhz operation
process
begin
clk <= '0';
wait for 3750 ps;
clk <= '1';
wait for 3750 ps;
end process;
process
begin
clk2 <= '0';
wait for 2750 ps;
clk2 <= '1';
wait for 3750 ps;
clk2 <= '0';
wait for 1000 ps;
end process;
-- clocks for 100mhz operations
-- process
-- begin
-- clk <= '0';
-- wait for 5000 ps;
-- clk <= '1';
-- wait for 5000 ps;
-- end process;
-- process
-- begin
-- clk2 <= '0';
-- wait for 4000 ps;
-- clk2 <= '1';
-- wait for 5000 ps;
-- clk2 <= '0';
-- wait for 1000 ps;
-- end process;
process
variable x : integer := 0;
variable j : integer := 0;
variable yi : integer := 0;
variable bl : integer := 0;
variable zi : integer := 0;
begin
reset_n <= '0';
wait for 100 ns;
reset_n <= '1';
wait for 200 ns;
report "Testing page burst accesses";
config("011", "11", 0, '1', x"05F6", addr, cmdack, cmd);
wait for 1000 ns;
report "Writing a ramp value from 0-29 out to sdram at address 0x0";
page_write_burst("00000000000000000000000", x"00000000", x"0", 3, 30, datain, addr, dm, cmd, cmdack);
wait for 1000 ns;
report "Reading the ramp value from sdram at address 0x0";
page_read_burst("00000000000000000000000", x"00000000", 3, 3, 30, addr, dataout, cmd, cmdack);
wait for 1000 ns;
report "Testing data mask inputs";
config("011", "11", 8, '0', x"05F6", addr, cmdack, cmd);
wait for 1000 ns;
report "writing pattern 0,1,2,3,4,5,6,7 to sdram at address 0x0";
burst_write(x"00000000", "00000000000000000000000", 8, 3, x"0", addr, datain, dm, cmdack, cmd);
wait for 1000 ns;
report "Reading and verifing the pattern 0,1,2,3,4,5,6,7 at sdram address 0x0";
burst_read(x"00000000", "00000000000000000000000", 8, 3, 3, addr, dataout, cmdack, cmd);
wait for 1000 ns;
report "Writing pattern 0xfffffff0, 0xfffffff1, 0xfffffff2, 0xfffffff3, 0xfffffff4, 0xfffffff5, 0xfffffff6, 0xfffffff7";
report "with DM set to 0xf";
burst_write(x"FFFFFFF0", "00000000000000000000000", 8, 3, x"f", addr, datain, dm, cmdack, cmd);
wait for 1000 ns;
report "Reading and verifing that the pattern at sdram address 0x0 is";
report "still 0,1,2,3,4,5,6,7";
burst_read(x"00000000", "00000000000000000000000", 8, 3, 3, addr, dataout, cmdack, cmd);
wait for 1000 ns;
report "End of data mask test";
report "running data pattern tests";
bl := 1;
for x in 1 to 4 loop -- step through the four burst lengths 1,2,4,8
y <= "011";
z <= "11";
for yi in 3 to 3 loop -- at 133mhz cl must be 3, if 100mhz cl can be 2
for zi in 3 to 3 loop -- at 133mhz rc must be 3, if 100mhz rc can be 2
config(y, z, bl, '0', x"05F6", addr, cmdack, cmd);
-- perform 1024 burst writes to the first chip select, writing a ramp pattern
report "Peforming burst write to first sdram bank";
test_data <= (others => '0');
test_addr <= (others => '0');
for j in 0 to 1024 loop
burst_write(test_data, test_addr, bl, zi, x"0", addr, datain, dm, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
wait for 100 ns;
end loop;
-- perform 1024 burst reads to the first chip select, verifing the ramp pattern
report "Performing burst read, verify ramp values in first sdram bank";
test_data <= (others => '0');
test_addr <= (others => '0');
for j in 0 to 1024 loop
burst_read(test_data, test_addr, bl, yi, zi, addr, dataout, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
end loop;
wait for 500 ns;
-- perform 1024 burst writes to the second chip select, writing a ramp pattern
report "Peforming burst write to second sdram bank";
test_data <= x"00400000";
test_addr <= "10000000000000000000000";
for j in 0 to 1024 loop
burst_write(test_data, test_addr, bl, zi, x"0", addr, datain, dm, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
wait for 100 ns;
end loop;
-- perform 1024 burst reads to the second chip select, verifing the ramp pattern
report "Performing burst read, verify ramp values in second sdram bank";
test_data <= x"00400000";
test_addr <= "10000000000000000000000";
for j in 0 to 1024 loop
burst_read(test_data, test_addr, bl, yi, zi, addr, dataout, cmdack, cmd);
test_data <= test_data + bl;
test_addr <= test_addr + bl;
end loop;
wait for 500 ns;
report "Test complete";
z <= z+1;
end loop;
y<=y+1;
end loop;
bl := bl * 2;
end loop;
assert false report "all tests complete" severity failure;
end process;
end rtl;
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