ctc_decoder_core.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_decoder_core.v
/// Author       : wangjinshan
/// Department   : 2nd IC department
/// Email        : [e-mail]
///
/// Module_name  : ctc_decoder_core
/// Called by    : ctc_decoder  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                      |----ctc_mctrl
/// ctc_decoder_core-----|----ctc_decoder_datapath_top
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-05-20  | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核顶层文件
///*********************************************************************

`timescale  1ns/100ps

module  ctc_decoder_core
    (
    ///interface with ctc_rx_fsm
    ///input
    input              core_gnt,                    ///应答信号
    input              wr_over,                     ///写dpram结束信号
    input       [15:0] rx2ctrl_length,              ///FEC译码块的长度
    input       [2:0]  rx2ctrl_type,                ///类型号
    input       [2:0]  rx2ctrl_frame_end_flag,      ///帧结束标志    //add by mahui 070704
    input       [1:0]  rx2ctrl_inst,                ///instance
    input       [2:0]  rx2ctrl_code_rate,           ///码率 000:HARQ 001:1/2 010:2/3 011:3/4
    input       [1:0]  rx2ctrl_modu_type,           ///00为QPSK，01为16QAM，10为64QAM
    input       [15:0] rx2ctrl_bnum,                ///突发号
    input       [7:0]  rx2ctrl_fnum,                ///FEC号
    input       [3:0]  rx2ctrl_miter,               ///最大迭代次数
    input       [3:0]  rx2ctrl_segId,             ///segment号
    ///output
    output wire        dec_finish,                  ///单译码块译码结束标记
    output wire        core_req,                    ///请求信号
    ///interface with ctc_dpram_1
    ///input
    input       [11:0] dpram1_rddat,                ///双口RAM的读数据
    ///output
    output wire [11:0] dpram1_rdadr,                ///存放译码数据的双口RAM地址
    output             dpram1_rd,                   ///双口RAM地址的读信号
    ///interface with ctc_dpram_2
    ///input
    input       [23:0] dpram2_rddat,                ///双口RAM的读数据
    ///output
    output wire [11:0] dpram2_rdadr,                ///存放译码数据的双口RAM地址
    output wire        dpram2_rd,                   ///双口RAM地址的读信号
    ///interface with ctc_fifo
    ///input
    input              ctc_fifo_empty,              ///FIFO空指示信号
    input              ctc_fifo_full,               ///FIFO满指示信号
    input       [8:0]  ctc_fifo_usedw,
    ///output
    output wire [31:0] ctc_fifo_wrdat,              ///FIFO写数据
    output wire        ctc_fifo_wrreq,              ///FIFO写信号
    ///system signals
    input              sys_clk,                     ///系统时钟信号
    input              reset_b                      ///输入复位信号
    );
///*********************************************************************
///内部信号定义
///*********************************************************************
wire    [23:0]  le;                                 ///外信息
wire            sop_sink;
wire            eop_sink;
wire            val_sink;
wire    [23:0]  la;                                 ///先验信息
wire    [11:0]  ys;
wire    [11:0]  yp;
wire            sop_source;
wire            eop_source;
wire            val_source;
wire    [11:0]  dat_addr;                           ///交织地址输出
wire    [11:0]  llrde_addr;                         ///外信息解交织地址
wire            mctrl2dat_en;                       ///交织/解交织地址计算使能信号
wire    [11:0]  mctrl2dat_addr;                     ///交织地址ram读地址
wire            mctrl2dat_rd;                       ///交织地址ram读信号
wire    [11:0]  mctrl2llrde_addr;                   ///外信息解交织地址ram读地址
wire            mctrl2llrde_rd;
wire            dec_end;                            ///迭代完成信号
wire    [3:0]   dec_no;                             ///迭代次数
wire    [15:0]  ctrl2resm_length;
wire    [2:0]   ctrl2resm_type;
wire    [2:0]   ctrl2resm_frame_end_flag;
wire    [1:0]   ctrl2resm_inst;
wire    [2:0]   ctrl2resm_code_rate;
wire    [1:0]   ctrl2resm_modu_type;
wire    [15:0]  ctrl2resm_bnum;
wire    [7:0]   ctrl2resm_fnum;
wire    [3:0]   ctrl2resm_miter;
wire    [3:0]   ctrl2resm_segId;

///*********************************************************************
///主程序代码：
///*********************************************************************
///主控模块
//主控模块
ctc_mctrl ctc_mctrl 
(
    .core_gnt                    (core_gnt                ),
    .wr_over                     (wr_over                 ),
    .rx2ctrl_length              (rx2ctrl_length          ),
    .rx2ctrl_type                (rx2ctrl_type            ),
    .rx2ctrl_frame_end_flag      (rx2ctrl_frame_end_flag  ),//帧结束标志    //add by mahui 070704
    .rx2ctrl_inst                (rx2ctrl_inst            ),                
    .rx2ctrl_code_rate           (rx2ctrl_code_rate       ),
    .rx2ctrl_modu_type           (rx2ctrl_modu_type       ),
    .rx2ctrl_bnum                (rx2ctrl_bnum            ),
    .rx2ctrl_fnum                (rx2ctrl_fnum            ),
    .rx2ctrl_miter               (rx2ctrl_miter           ),
    .rx2ctrl_segId               (rx2ctrl_segId           ),//add by mahui 070704
    .dec_finish                  (dec_finish              ),
    .core_req                    (core_req                ),
    .dpram1_rddat                (dpram1_rddat            ),
    .dpram1_rdadr                (dpram1_rdadr            ),
    .dpram1_rd                   (dpram1_rd               ),
    .dpram2_rddat                (dpram2_rddat            ),
    .dpram2_rdadr                (dpram2_rdadr            ),
    .dpram2_rd                   (dpram2_rd               ),
    .le                          (le                      ),
    .sop_sink                    (sop_sink                ),
    .eop_sink                    (eop_sink                ),
    .val_sink                    (val_sink                ),
    .la                          (la                      ),
    .ys                          (ys                      ),
    .yp                          (yp                      ),
    .sop_source                  (sop_source              ),
    .eop_source                  (eop_source              ),
    .val_source                  (val_source              ),
    .dat_addr                    (dat_addr                ),
    .llrde_addr                  (llrde_addr              ),
    .mctrl2dat_en                (mctrl2dat_en            ),
    .mctrl2dat_addr              (mctrl2dat_addr          ),
    .mctrl2dat_rd                (mctrl2dat_rd            ),
    .mctrl2llrde_addr            (mctrl2llrde_addr        ),
    .mctrl2llrde_rd              (mctrl2llrde_rd          ),
    .dec_end                     (dec_end                 ),
    .dec_no                      (dec_no                  ),
    .ctrl2resm_length            (ctrl2resm_length        ),
    .ctrl2resm_type              (ctrl2resm_type          ),
    .ctrl2resm_frame_end_flag    (ctrl2resm_frame_end_flag),//帧结束标志    //add by mahui 070704
    .ctrl2resm_inst              (ctrl2resm_inst          ),            
    .ctrl2resm_code_rate         (ctrl2resm_code_rate     ),
    .ctrl2resm_modu_type         (ctrl2resm_modu_type     ),
    .ctrl2resm_bnum              (ctrl2resm_bnum          ),
    .ctrl2resm_fnum              (ctrl2resm_fnum          ),
    .ctrl2resm_miter             (ctrl2resm_miter         ),
    .ctrl2resm_segId             (ctrl2resm_segId         ),//add by mahui 070704
    .sys_clk                     (sys_clk                 ),
    .reset_b                     (reset_b                 )
);    

ctc_decoder_datapath_top ctc_decoder_datapath_top
    (
    //system i/f 
    .clk_sys               (sys_clk                 ),
    .rst_b                 (reset_b                 ),
    //MAX-LOG-MAP input i/f                         
    .ys                    (ys                      ),
    .yp                    (yp                      ),
    .la                    (la                      ),
    .sop_source            (sop_source              ),
    .eop_source            (eop_source              ),
    .val_source            (val_source              ),
    //MAX-LOG-MAP output i/f
    .le                    (le                      ),
    .sop_sink              (sop_sink                ),
    .eop_sink              (eop_sink                ),
    .val_sink              (val_sink                ),
    //iter_stop i/f
    .iter_stop             (dec_end                 ),
    //packet para i/f                               
    .packet_type           (ctrl2resm_type          ),
    .packet_frame_end_flag (ctrl2resm_frame_end_flag),//add by mahui 070704
    .instance_num          (ctrl2resm_inst          ),
    .packet_length         (ctrl2resm_length        ),
    .code_rate             (ctrl2resm_code_rate     ),
    .modulate_type         (ctrl2resm_modu_type     ),
    .burst_id              (ctrl2resm_bnum          ),
    .fec_id                (ctrl2resm_fnum          ),
    .max_iter_no           (ctrl2resm_miter         ),
    .segId                 (ctrl2resm_segId         ),//add by mahui 070704
    //output fifo i/f
    .fifo_usedword         (ctc_fifo_usedw          ),
    .dat_wr_fifo           (ctc_fifo_wrdat          ),
    .wr_fifo               (ctc_fifo_wrreq          ),
    //int/deint adr gen i/f
    .int_deint_adr_gen_en  (mctrl2dat_en            ),
    .rd_int_ram0           (mctrl2dat_rd            ),
    .adr_rd_int_ram0       (mctrl2dat_addr          ),
    .dat_rd_int_ram0       (dat_addr                ),
    .rd_deint_ram0         (mctrl2llrde_rd          ),
    .adr_rd_deint_ram0     (mctrl2llrde_addr        ),
    .dat_rd_deint_ram0     (llrde_addr              )
    );
                                                                                                
   endmodule