llr_max4.v

上传的是WIMAX系统中

//FILE_HEADER------------------------------------------------------------------
//Copyright: 2006 ZTE CORPORATION
//Company Confidential: This proprietary may be used only as authorized by a 
//                      agreement from WiMAX Department of ZTE CORPORATION.  
//----------------------------------------------------------------------------
//FILENAME       : llr_max4.v
//DEPARTMENT     : WiMAX department
//AUTHOR         : yuanliuqing
//AUTHOR'S EMAIL : [e-mail]
//----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION      DATE         AUTHOR       DESCRIPTION
// 0.1       2006-6-16     yuanliuqing   create
//---------------------------------------------------------------------------- 
//KEYWORDS       : max
//----------------------------------------------------------------------------
//PURPOSE        : select maximum number of 4 numbers, pure combinational logic.
//----------------------------------------------------------------------------
//PARAMETERS    
//PARAM NAME:        RANGE:            DESCRIPTION:        DEFAULT:   UNITS:
//
//----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy     : N/A
//Clock  Domains     : N/A
//Critical Timing    : N/A
//Test   Features    : N/A
//Asynchronous I/F   : N/A
//Scan Methodology   : Mux-D
//Instaniations      : N/A
//Synthesizable      : Yes
//Other              : N/A
//END_HEADER------------------------------------------------------------------

`timescale 1ns/100ps

module llr_max4
    (
        //system i/f
        clk_sys,
        rst_b,    
        //input i/f
        a,
        b,
        c,
        d,
        //output i/f
        z
    );
    //*************************************************************************
    parameter DATA_WIDTH = 6'd12;
    //*************************************************************************
    //ports direction
    //system i/f 
    input   clk_sys;        //system clock
    input   rst_b;          //reset signal, low valid
    //input i/f
    input   [DATA_WIDTH-1:0]  a;
    input   [DATA_WIDTH-1:0]  b;
    input   [DATA_WIDTH-1:0]  c;
    input   [DATA_WIDTH-1:0]  d;
    //output i/f
    output  [DATA_WIDTH-1:0]  z;
    //*************************************************************************
    //ports type
    //system i/f 
    wire    clk_sys;        //system clock
    wire    rst_b;          //reset signal, low valid    
    //input i/f
    wire    [DATA_WIDTH-1:0]  a;
    wire    [DATA_WIDTH-1:0]  b;
    wire    [DATA_WIDTH-1:0]  c;
    wire    [DATA_WIDTH-1:0]  d;
    //output i/f
    reg     [DATA_WIDTH-1:0]  z;
    //*************************************************************************
    
    //wire    [DATA_WIDTH-1:0]  aa,bb;
    //wire    [DATA_WIDTH-1:0]  r1,r2,r3;

    //************************************************************
    // all variables are signed
    // mod_max
    //************************************************************
        
//    assign  r1 = a-b;
//    assign  r2 = c-d;
//    assign  r3 = aa-bb;
/*
    sub12 sub12_u1
    (
    	.dataa   (a),
    	.datab   (b),
    	.result  (r1)
	);

    sub12 sub12_u2
    (
    	.dataa   (c),
    	.datab   (d),
    	.result  (r2)
	);
	
    sub12 sub12_u3
    (
    	.dataa   (aa),
    	.datab   (bb),
    	.result  (r3)
	);
	    
    assign  aa = (!r1[DATA_WIDTH-1])?a:b;
    assign  bb = (!r2[DATA_WIDTH-1])?c:d;


//    assign  z  = (!r3[DATA_WIDTH-1])?aa:bb;
    
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    z  <= 12'd0;
                end
            else  
                begin
                    z  <= (!r3[DATA_WIDTH-1])?aa:bb;
                end
        end
        
*/
  wire    [DATA_WIDTH-1:0]   r0,r1,r2,r3,r4,r5;
  assign r0 = a - b;
  assign r1 = a - c;
  assign r2 = a - d;
  assign r3 = b - c;
  assign r4 = b - d;
  assign r5 = c - d;
  
  wire[5:0] aa = {r0[DATA_WIDTH-1], r1[DATA_WIDTH-1],
                  r2[DATA_WIDTH-1], r3[DATA_WIDTH-1],
                  r4[DATA_WIDTH-1], r5[DATA_WIDTH-1]};
  
  
  always @( posedge clk_sys or negedge rst_b )
    if(!rst_b)
      z  <= 12'd0;
    else
      casex (aa)
	    6'b000xxx : z <= a;
	    6'b1xx00x : z <= b;
	    6'bx1x1x0 : z <= c;
//	    6'bxx1x11 : z <= d;
	    default   : z <= d;
      endcase


//    reg    [DATA_WIDTH-1:0]   r0,r1,r2,r3,r4,r5; 
//    always @( posedge clk_sys or negedge rst_b )
//        if(!rst_b) begin
//            r0 <= 1'b0; 
//            r1 <= 1'b0;
//            r2 <= 1'b0;
//            r3 <= 1'b0;
//            r4 <= 1'b0;
//            r5 <= 1'b0;
//        end
//        else begin
//            r0 <= a - b;
//            r1 <= a - c;
//            r2 <= a - d;
//            r3 <= b - c;
//            r4 <= b - d;
//            r5 <= c - d;
//        end
//    reg   [5:0]     aa;
//    always @(*) begin
//        aa = {r0[DATA_WIDTH-1], r1[DATA_WIDTH-1],  
//              r2[DATA_WIDTH-1], r3[DATA_WIDTH-1], 
//              r4[DATA_WIDTH-1], r5[DATA_WIDTH-1]};
//        casex (aa)             
//            6'b000xxx : z = a;
//            6'b1xx00x : z = b;
//            6'bx1x1x0 : z = c;
//            default   : z = d;  
//        endcase 
//    end               
//







        
endmodule