max_log_map.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : max_log_map.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : max_log_map
/// Called by    : ctc_decoder_datapath_top  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                 |----l_le_hd_cal
///                 |----alpha_buf
///                 |----block_cir_buf
/// max_log_map-----|----alpha_cal
///                 |----beta_cal0
///                 |----beta_cal1
///                 |----sliding_win_fsm
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-13  | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核max-log-map计算单元
///*********************************************************************

`timescale 1ns/100ps

module max_log_map
    #(parameter SOFT_INFO_WIDTH  = 6'd6,                ///软信息数据宽度
                PRIOR_INFO_WIDTH = 6'd8,                ///先验信息数据宽度
                HD_DAT_WIDTH     = 6'd2,                ///dual binary
                BRANCH_MATRIC_WIDTH = 6'd9,             ///分支度量数据宽度
                STATE_MATRIC_WIDTH = 6'd12,             ///状态度量数据宽度
                LLR_INFO_WIDTH = 6'd12      )           ///对数似然比数据宽度
    (
    ///system i/f
    input              clk_sys,                         ///系统时钟信号
    input              rst_b,                           ///输入复位信号
    ///input i/f
    input       [SOFT_INFO_WIDTH*2-1:0]   ys,           ///soft info: system part
    input       [SOFT_INFO_WIDTH*2-1:0]   yp,           ///soft info: check part
    input       [PRIOR_INFO_WIDTH*3-1:0]  la,           ///prior info
    input                                 sop_source,   ///start of source packet(not window)
    input                                 eop_source,   ///end of source packet(not window)
    input                                 val_source,   ///source data valid
    input       [15:0]                    packet_length,
    ///output i/f
    output wire [HD_DAT_WIDTH-1:0]        d,            ///output hard-decision data
    output wire [PRIOR_INFO_WIDTH*3-1:0]  le,           ///output extrinsic info
    output wire [LLR_INFO_WIDTH*3-1:0]    l,            ///output bit-pair llr
    output wire                           sop_sink,     ///start of sink packet(not window)
    output wire                           eop_sink,     ///end of sink packet(not window)
    output wire                           val_sink      ///sink data valid
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
    wire                                clr_cal_buf;

///*********************************************************************
///component code decoder data path
///*********************************************************************
    
    wire                                rd_cir_buf_cell0,rd_cir_buf_cell1,rd_cir_buf_cell2;
    reg                                 rd_cir_buf_cell1_d1,rd_cir_buf_cell2_d1;
    wire    [PRIOR_INFO_WIDTH-1:0]      la23,la22,la21, la13,la12,la11, la03,la02,la01;
    wire    [SOFT_INFO_WIDTH-1:0]       yp21,yp20,ys21,ys20, yp11,yp10,ys11,ys10, yp01,yp00,ys01,ys00;
    reg     [PRIOR_INFO_WIDTH-1:0]      la23_d1,la22_d1,la21_d1, la13_d1,la12_d1,la11_d1;
    reg     [SOFT_INFO_WIDTH-1:0]       yp21_d1,yp20_d1,ys21_d1,ys20_d1, yp11_d1,yp10_d1,ys11_d1,ys10_d1;    

///*********************************************************************
///主程序代码：
///*********************************************************************
///block circular buffer
    block_cir_buf block_cir_buf
    (
        ///system i/f    
        .clk_sys          (clk_sys                             ),
        .rst_b            (rst_b                               ),
        ///input i/f                                            
        .ys               (ys                                  ),
        .yp               (yp                                  ),
        .la               (la                                  ),
        .sop_source       (sop_source                          ),
        .eop_source       (eop_source                          ),
        .val_source       (val_source                          ),
        .clr_cir_buf      (clr_cal_buf                         ),
        ///output i/f                                           
        .rd_cir_buf_cell0 (rd_cir_buf_cell0                    ),
        .rd_cir_buf_cell1 (rd_cir_buf_cell1                    ),
        .rd_cir_buf_cell2 (rd_cir_buf_cell2                    ),
        .output_dat0      ({la03,la02,la01,yp01,yp00,ys01,ys00}),
        .output_dat1      ({la13,la12,la11,yp11,yp10,ys11,ys10}),
        .output_dat2      ({la23,la22,la21,yp21,yp20,ys21,ys20})
     );

    reg                                alpha_source_val;
    wire   [STATE_MATRIC_WIDTH-1:0]    alpha7,alpha6,alpha5,alpha4,alpha3,alpha2,alpha1,alpha0;
    wire                               alpha_sink_val;
    reg                                beta_source_val0,beta_source_val1;
    wire   [STATE_MATRIC_WIDTH-1:0]    beta07,beta06,beta05,beta04,beta03,beta02,beta01,beta00,
                                       beta17,beta16,beta15,beta14,beta13,beta12,beta11,beta10;
    wire   [BRANCH_MATRIC_WIDTH-1:0]   gamma015,gamma014,gamma013,gamma012,gamma011,gamma010,gamma009,gamma008,
                                       gamma007,gamma006,gamma005,gamma004,gamma003,gamma002,gamma001,gamma000,
                                       gamma115,gamma114,gamma113,gamma112,gamma111,gamma110,gamma109,gamma108,
                                       gamma107,gamma106,gamma105,gamma104,gamma103,gamma102,gamma101,gamma100;
    wire                               beta_sink_val0,beta_sink_val1;
    wire                               new_beta_cal0,new_beta_cal1;
    wire   [SOFT_INFO_WIDTH-1:0]       ys01_beta_out,ys00_beta_out,ys11_beta_out,ys10_beta_out;
    wire   [PRIOR_INFO_WIDTH-1:0]      la03_beta_out,la02_beta_out,la01_beta_out,
                                       la13_beta_out,la12_beta_out,la11_beta_out;
    
///delay alpha_cal input 1 cycle for aligning with alpha_buf output
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        {la23_d1,la22_d1,la21_d1,yp21_d1,yp20_d1,ys21_d1,ys20_d1} <= 1'b0;
        {la13_d1,la12_d1,la11_d1,yp11_d1,yp10_d1,ys11_d1,ys10_d1} <= 1'b0;
    end
    else begin
        {la23_d1,la22_d1,la21_d1,yp21_d1,yp20_d1,ys21_d1,ys20_d1}
            <= {la23,la22,la21,yp21,yp20,ys21,ys20};
        {la13_d1,la12_d1,la11_d1,yp11_d1,yp10_d1,ys11_d1,ys10_d1}
            <= {la13,la12,la11,yp11,yp10,ys11,ys10};
    end
end

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        alpha_source_val <= 1'b0;
        beta_source_val1 <= 1'b0;
        beta_source_val0 <= 1'b0;
        rd_cir_buf_cell1_d1 <= 1'b0;
        rd_cir_buf_cell2_d1 <= 1'b0;
    end
    else begin
        alpha_source_val <= rd_cir_buf_cell0;
        beta_source_val1 <= rd_cir_buf_cell2_d1;
        beta_source_val0 <= rd_cir_buf_cell1_d1;
        rd_cir_buf_cell1_d1 <= rd_cir_buf_cell1;
        rd_cir_buf_cell2_d1 <= rd_cir_buf_cell2;
    end
end
 
    ///{la,yp,ys}
    ///alpha calculator    
    alpha_cal alpha_cal
    (
        ///system i/f    
        .clk_sys          (clk_sys                                                  ),
        .rst_b            (rst_b                                                    ),
        ///input i/f                                                                 
        .ys               ({ys01,ys00}                                              ),
        .yp               ({yp01,yp00}                                              ),
        .la               ({la03,la02,la01}                                         ),
        .alpha_source_val (alpha_source_val                                         ),
        .clr_alpha        (clr_cal_buf),
        ///output i/f
        .alpha            ({alpha7,alpha6,alpha5,alpha4,alpha3,alpha2,alpha1,alpha0}),
        .alpha_sink_val   (alpha_sink_val                                           )
    );
        
    ///beta calculator 0
    beta_cal beta_cal0