📄 int_deint_adr_gen.v
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///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name : int_deint_adr_gen.v
/// Author : yuanliuqing
/// Department : WiMAX department
/// Email : yuan.liuqing@zte.com.cn
///
/// Module_name : int_deint_adr_gen
/// Called by : ctc_decoder_datapath_top module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// |----int_adr_ram_u
/// |----int_deint_adr_gen_mul
/// int_deint_adr_gen-----|----int_deint_adr_gen_para_rom
/// |----int_deint_adr_gen_div
/// |----deint_adr_ram_u
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version | Date | Author Description
///---------------------------------------------------------------------
/// 1.0-0 | 2006-06-22 | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核交织解交织地址单元
///*********************************************************************
`timescale 1ns/100ps
module int_deint_adr_gen
(
///system i/f
input clk_sys, ///系统时钟信号
input rst_b, ///输入复位信号
///input i/f
input int_deint_adr_gen_en, ///交织/解交织地址计算使能
input [15:0] packet_length, ///包长
///output i/f
input rd_int_ram0, ///交织地址ram0读信号
input [11:0] adr_rd_int_ram0, ///交织地址ram0读地址
output wire [11:0] dat_rd_int_ram0, ///交织地址ram0输出数据线
input rd_int_ram1, ///交织地址ram1读信号
input [11:0] adr_rd_int_ram1, ///交织地址ram1读地址
output wire [11:0] dat_rd_int_ram1, ///交织地址ram1输出数据线
input rd_deint_ram0, ///解交织地址ram0读信号
input [11:0] adr_rd_deint_ram0, ///解交织地址ram0读地址
output wire [11:0] dat_rd_deint_ram0, ///解交织地址ram0输出数据线
input rd_deint_ram1, ///解交织地址ram1读信号
input [11:0] adr_rd_deint_ram1, ///解交织地址ram1读地址
output wire [11:0] dat_rd_deint_ram1 ///解交织地址ram1输出数据线
);
///*********************************************************************
///内部信号定义
///*********************************************************************
reg [15:0] packet_length_buf;
reg [15:0] packet_length_buf_1;
reg [4:0] adr_rd_para_rom;
reg [11:0] adr_gen_counter;
reg adr_gen_counter_val;
//buffer packet_length
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
packet_length_buf <= 1'b0;
else if( int_deint_adr_gen_en )
packet_length_buf <= packet_length;
else
packet_length_buf <= packet_length_buf;
end
///fyz修改，为了对准时序
// assign packet_length_buf_2 = int_deint_adr_gen_en ? packet_length : packet_length_buf_2;
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
packet_length_buf_1 <= 1'b0;
else if( int_deint_adr_gen_en )
packet_length_buf_1 <= (packet_length>>1'b1);
else
packet_length_buf_1 <= packet_length_buf_1;
end
reg int_deint_adr_gen_en_d1;
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
int_deint_adr_gen_en_d1 <= 1'b0;
else
int_deint_adr_gen_en_d1 <= int_deint_adr_gen_en;
end
always @ ( posedge clk_sys or negedge rst_b )
if ( !rst_b )
adr_rd_para_rom <= 5'd0;
else
case( packet_length_buf )
16'd24:
adr_rd_para_rom <= 5'd0;
16'd36:
adr_rd_para_rom <= 5'd1;
16'd48:
adr_rd_para_rom <= 5'd2;
16'd72:
adr_rd_para_rom <= 5'd3;
16'd96:
adr_rd_para_rom <= 5'd4;
16'd108:
adr_rd_para_rom <= 5'd5;
16'd120:
adr_rd_para_rom <= 5'd6;
16'd144:
adr_rd_para_rom <= 5'd7;
16'd180:
adr_rd_para_rom <= 5'd8;
16'd192:
adr_rd_para_rom <= 5'd9;
16'd216:
adr_rd_para_rom <= 5'd10;
16'd240:
adr_rd_para_rom <= 5'd11;
16'd480:
adr_rd_para_rom <= 5'd12;
16'd960:
adr_rd_para_rom <= 5'd13;
16'd1440:
adr_rd_para_rom <= 5'd14;
16'd1920:
adr_rd_para_rom <= 5'd15;
16'd2400:
adr_rd_para_rom <= 5'd16;
default:
adr_rd_para_rom <= 5'd0;
endcase
wire [5:0] p0;
wire [9:0] p1,p2,p3;
//int_deint_adr_gen_para_rom parameter: 36-b dat, 5-b adr, no output register
///p0,p1,p2,p3的产生延迟1 cycle，和adr_gen_counter同时有效
int_deint_adr_gen_para_rom int_deint_adr_gen_para_rom
(
.address (adr_rd_para_rom),
.clock (clk_sys ),
.q ({p0,p1,p2,p3} )
);
//*************************************************************************
//int/deint adr gen fsm
//*************************************************************************
parameter READY = 2'b01,
RUN = 2'b10;
reg [1:0] adr_gen_state_current;
reg [1:0] adr_gen_state_next;
//int/deint adr gen fsm
always @ ( posedge clk_sys or negedge rst_b )
if( !rst_b )
adr_gen_state_current <= READY;
else
adr_gen_state_current <= adr_gen_state_next;
always @ ( * )
begin
case( adr_gen_state_current )
READY:
if( int_deint_adr_gen_en && !int_deint_adr_gen_en_d1 )
adr_gen_state_next = RUN;
else
adr_gen_state_next = READY;
RUN:
if( adr_gen_counter == (packet_length_buf[11:0]-2'd2) )
adr_gen_state_next = READY;
else
adr_gen_state_next = RUN;
default:
adr_gen_state_next = READY;
endcase
end
//reg [11:0] adr_gen_counter;
//generate adr_gen_counter
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
adr_gen_counter <= 1'b0;
else
case( adr_gen_state_current )
READY:
adr_gen_counter <= 1'b0;
RUN:
if( adr_gen_counter_val )
adr_gen_counter <= adr_gen_counter + 1'b1;
else
adr_gen_counter <= adr_gen_counter;
default:
adr_gen_counter <= 1'b0;
endcase
end
//reg adr_gen_counter_val;
//generate adr_gen_counter_val
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
adr_gen_counter_val <= 1'b0;
else
case( adr_gen_state_current )
READY:
adr_gen_counter_val <= 1'b0;
RUN:
adr_gen_counter_val <= 1'b1;
default:
adr_gen_counter_val <= 1'b0;
endcase
end
//*************************************************************************
//data path for generating int/deint adr
//*************************************************************************
reg [11:0] adr_gen_counter_d6,adr_gen_counter_d5,adr_gen_counter_d4,adr_gen_counter_d3,adr_gen_counter_d2,adr_gen_counter_d1;
reg [11:0] adr_gen_counter_d12,adr_gen_counter_d11,adr_gen_counter_d10,adr_gen_counter_d9,adr_gen_counter_d8,adr_gen_counter_d7;
reg [11:0] adr_gen_counter_d17,adr_gen_counter_d16,adr_gen_counter_d15,adr_gen_counter_d14,adr_gen_counter_d13;
reg [17:0] adr_gen_counter_val_d;
//data path for generating int/deint adr
//delay adr_gen_counter 9 cycles according adr_gen pipeline delay
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
{ adr_gen_counter_d17,adr_gen_counter_d16,
adr_gen_counter_d15,adr_gen_counter_d14,adr_gen_counter_d13,
adr_gen_counter_d12,adr_gen_counter_d11,adr_gen_counter_d10,
adr_gen_counter_d9,adr_gen_counter_d8,adr_gen_counter_d7,
adr_gen_counter_d6,adr_gen_counter_d5,adr_gen_counter_d4,
adr_gen_counter_d3,adr_gen_counter_d2,adr_gen_counter_d1 } <= 1'b0;
else
{ adr_gen_counter_d17,adr_gen_counter_d16,
adr_gen_counter_d15,adr_gen_counter_d14,adr_gen_counter_d13,
adr_gen_counter_d12,adr_gen_counter_d11,adr_gen_counter_d10,
adr_gen_counter_d9,adr_gen_counter_d8,adr_gen_counter_d7,
adr_gen_counter_d6,adr_gen_counter_d5,adr_gen_counter_d4,
adr_gen_counter_d3,adr_gen_counter_d2,adr_gen_counter_d1 }
<=
{ adr_gen_counter_d16,
adr_gen_counter_d15,adr_gen_counter_d14,adr_gen_counter_d13,
adr_gen_counter_d12,adr_gen_counter_d11,adr_gen_counter_d10,
adr_gen_counter_d9,adr_gen_counter_d8,adr_gen_counter_d7,
adr_gen_counter_d6,adr_gen_counter_d5,adr_gen_counter_d4,
adr_gen_counter_d3,adr_gen_counter_d2,adr_gen_counter_d1,
adr_gen_counter };
end
//delay adr_gen_counter_val 9 cycles according adr_gen pipeline delay
always @ ( posedge clk_sys or negedge rst_b )
begin
if( !rst_b )
adr_gen_counter_val_d <= READY;
else
adr_gen_counter_val_d <= { adr_gen_counter_val_d[16:0], adr_gen_counter_val };
end
wire [17:0] mul_result;
//mul, 2 cycles pipeline
int_deint_adr_gen_mul int_deint_adr_gen_mul
(
.aclr (!rst_b ),
.clock (clk_sys ),
.dataa (adr_gen_counter),
.datab (p0 ),
.result (mul_result )
);
reg [18:0] add_result;
//add, comb logic
///时序逻辑，增加2 cycle
reg [17:0] add_1, add_2, add_3, add_4;
reg [15:0] add_5;
always @ ( posedge clk_sys or negedge rst_b )
if(!rst_b) begin
add_1 <= 18'd0;
add_2 <= 18'd0;
add_3 <= 18'd0;
add_4 <= 18'd0;
add_5 <= 16'd0;
end
else begin
add_1 <= mul_result ;
add_2 <= mul_result + p1;
add_3 <= mul_result + p2;
add_4 <= mul_result + p3;
add_5 <= (packet_length_buf>>1'b1) + 1'b1;
end
always @ ( posedge clk_sys or negedge rst_b )
if ( !rst_b )
add_result <= 1'b0;
else
case( adr_gen_counter_d3[1:0] )
2'b00:
add_result <= add_1 + 1'b1;
2'b01:
add_result <= add_2 + add_5;
2'b10:
add_result <= add_3 + 1'b1;
2'b11:
add_result <= add_4 + add_5;
default:
add_result <= 1'b0;
endcase
wire [11:0] mod_result;
//mod, 7 cycles pipeline ///原来程序中注明6 cycle，实际调用的是7 cycle
//mod, 13 cycles pipeline, fyz ///此处增加了6 cycle
int_deint_adr_gen_div int_deint_adr_gen_div
(
.aclr (!rst_b ),
.clock (clk_sys ),
.denom (packet_length_buf[11:0]),
.numer (add_result ),
.quotient ( ),
.remain (mod_result )
);
//**************************************************
wire [11:0] address1,address2;
assign address1 = (adr_gen_counter_val_d[16])?adr_gen_counter_d17:adr_rd_int_ram0;
assign address2 = (adr_gen_counter_val_d[16])?mod_result:adr_rd_deint_ram0;
int_deint_adr_ram int_adr_ram_u
(
.address_a (address1 ),
.address_b (adr_rd_int_ram1 ),
.clock (clk_sys ),
.data_a (mod_result ),
.data_b (12'b0 ),
.wren_a (adr_gen_counter_val_d[16]),
.wren_b (1'b0 ),
.q_a (dat_rd_int_ram0 ),
.q_b (dat_rd_int_ram1 )
);
int_deint_adr_ram deint_adr_ram_u
(
.address_a (address2 ),
.address_b (adr_rd_deint_ram1 ),
.clock (clk_sys ),
.data_a (adr_gen_counter_d17 ),
.data_b (12'b0 ),
.wren_a (adr_gen_counter_val_d[16]),
.wren_b (1'b0 ),
.q_a (dat_rd_deint_ram0 ),
.q_b (dat_rd_deint_ram1 )
);
endmodule ///int_deint_adr_gen
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