alpha_cal.v

上传的是WIMAX系统中

reg [BRANCH_MATRIC_WIDTH-1:0] gamma15,gamma14,gamma13,gamma12,
                              gamma11,gamma10,gamma9, gamma8,
                              gamma7, gamma6, gamma5, gamma4,
                              gamma3, gamma2, gamma1, gamma0;

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        { gamma15, gamma14, gamma13, gamma12,
            gamma11, gamma10, gamma9, gamma8,
                gamma7, gamma6, gamma5, gamma4,
                    gamma3, gamma2, gamma1, gamma0 }
                        <= 1'b0;
    end
    else if( clr_alpha ) begin
            { gamma15, gamma14, gamma13, gamma12,
                gamma11, gamma10, gamma9, gamma8,
                    gamma7, gamma6, gamma5, gamma4,
                        gamma3, gamma2, gamma1, gamma0 }
                            <= 1'b0;
        end
        else if( alpha_source_val_d2 ) begin
            { gamma15, gamma14, gamma13, gamma12,
                gamma11, gamma10, gamma9, gamma8,
                    gamma7, gamma6, gamma5, gamma4,
                        gamma3, gamma2, gamma1, gamma0 }
                            <=
            { gamma15_t2, gamma14_t2, gamma13_t2, gamma12_t2,
                gamma11_t2, gamma10_t2, gamma9_t2, gamma8_t2,
                    gamma7_t2, gamma6_t2, gamma5_t2, gamma4_t2,
                        gamma3_t2, gamma2_t2, gamma1_t2, gamma0_t2 };
        end
        else begin
            { gamma15, gamma14, gamma13, gamma12,
                gamma11, gamma10, gamma9, gamma8,
                    gamma7, gamma6, gamma5, gamma4,
                        gamma3, gamma2, gamma1, gamma0 }
                            <=
            { gamma15, gamma14, gamma13, gamma12,
                gamma11, gamma10, gamma9, gamma8,
                    gamma7, gamma6, gamma5, gamma4,
                        gamma3, gamma2, gamma1, gamma0 };
        end
end

///************************************************************************
///alpha calculator
///************************************************************************
wire [STATE_MATRIC_WIDTH-1:0] alpha00,alpha01,alpha02,alpha03,
                              alpha10,alpha11,alpha12,alpha13,
                              alpha20,alpha21,alpha22,alpha23,
                              alpha30,alpha31,alpha32,alpha33,
                              alpha40,alpha41,alpha42,alpha43,
                              alpha50,alpha51,alpha52,alpha53,
                              alpha60,alpha61,alpha62,alpha63,
                              alpha70,alpha71,alpha72,alpha73;

///alpha cal: natural overflow, modulo normaliztion
///gamma: sign extension
///cal alpha0
assign  alpha00 = alpha0 + {{3{gamma0[BRANCH_MATRIC_WIDTH-1]}},gamma0};
assign  alpha01 = alpha6 + {{3{gamma6[BRANCH_MATRIC_WIDTH-1]}},gamma6};
assign  alpha02 = alpha1 + {{3{gamma11[BRANCH_MATRIC_WIDTH-1]}},gamma11};
assign  alpha03 = alpha7 + {{3{gamma13[BRANCH_MATRIC_WIDTH-1]}},gamma13};
///cal alpha1
assign  alpha10 = alpha2 + {{3{gamma2[BRANCH_MATRIC_WIDTH-1]}},gamma2};
assign  alpha11 = alpha4 + {{3{gamma4[BRANCH_MATRIC_WIDTH-1]}},gamma4};
assign  alpha12 = alpha3 + {{3{gamma9[BRANCH_MATRIC_WIDTH-1]}},gamma9};
assign  alpha13 = alpha5 + {{3{gamma15[BRANCH_MATRIC_WIDTH-1]}},gamma15};
///cal alpha2
assign  alpha20 = alpha5 + {{3{gamma3[BRANCH_MATRIC_WIDTH-1]}},gamma3};
assign  alpha21 = alpha3 + {{3{gamma5[BRANCH_MATRIC_WIDTH-1]}},gamma5};
assign  alpha22 = alpha4 + {{3{gamma8[BRANCH_MATRIC_WIDTH-1]}},gamma8};
assign  alpha23 = alpha2 + {{3{gamma14[BRANCH_MATRIC_WIDTH-1]}},gamma14};
///cal alpha3
assign  alpha30 = alpha7 + {{3{gamma1[BRANCH_MATRIC_WIDTH-1]}},gamma1};
assign  alpha31 = alpha1 + {{3{gamma7[BRANCH_MATRIC_WIDTH-1]}},gamma7};
assign  alpha32 = alpha6 + {{3{gamma10[BRANCH_MATRIC_WIDTH-1]}},gamma10};
assign  alpha33 = alpha0 + {{3{gamma12[BRANCH_MATRIC_WIDTH-1]}},gamma12};
///cal alpha4
assign  alpha40 = alpha1 + {{3{gamma0[BRANCH_MATRIC_WIDTH-1]}},gamma0};
assign  alpha41 = alpha7 + {{3{gamma6[BRANCH_MATRIC_WIDTH-1]}},gamma6};
assign  alpha42 = alpha0 + {{3{gamma11[BRANCH_MATRIC_WIDTH-1]}},gamma11};
assign  alpha43 = alpha6 + {{3{gamma13[BRANCH_MATRIC_WIDTH-1]}},gamma13};
///cal alpha5
assign  alpha50 = alpha3 + {{3{gamma2[BRANCH_MATRIC_WIDTH-1]}},gamma2};
assign  alpha51 = alpha5 + {{3{gamma4[BRANCH_MATRIC_WIDTH-1]}},gamma4};
assign  alpha52 = alpha2 + {{3{gamma9[BRANCH_MATRIC_WIDTH-1]}},gamma9};
assign  alpha53 = alpha4 + {{3{gamma15[BRANCH_MATRIC_WIDTH-1]}},gamma15};
///cal alpha6
assign  alpha60 = alpha4 + {{3{gamma3[BRANCH_MATRIC_WIDTH-1]}},gamma3};
assign  alpha61 = alpha2 + {{3{gamma5[BRANCH_MATRIC_WIDTH-1]}},gamma5};
assign  alpha62 = alpha5 + {{3{gamma8[BRANCH_MATRIC_WIDTH-1]}},gamma8};
assign  alpha63 = alpha3 + {{3{gamma14[BRANCH_MATRIC_WIDTH-1]}},gamma14};
///cal alpha7
assign  alpha70 = alpha6 + {{3{gamma1[BRANCH_MATRIC_WIDTH-1]}},gamma1};
assign  alpha71 = alpha0 + {{3{gamma7[BRANCH_MATRIC_WIDTH-1]}},gamma7};
assign  alpha72 = alpha7 + {{3{gamma10[BRANCH_MATRIC_WIDTH-1]}},gamma10};
assign  alpha73 = alpha1 + {{3{gamma12[BRANCH_MATRIC_WIDTH-1]}},gamma12};

wire    [STATE_MATRIC_WIDTH-1:0]  alpha_t7,alpha_t6,alpha_t5,alpha_t4,
                                  alpha_t3,alpha_t2,alpha_t1,alpha_t0;

mod_max4 mod_max4_0
(
    ///input
    .a (alpha00 ),
    .b (alpha01 ),
    .c (alpha02 ),
    .d (alpha03 ),
    ///output
    .e (alpha_t0)
);

mod_max4 mod_max4_1
(
    ///input
    .a (alpha10 ),
    .b (alpha11 ),
    .c (alpha12 ),
    .d (alpha13 ),
    ///output
    .e (alpha_t1)
);

mod_max4 mod_max4_2
(
    ///input
    .a (alpha20 ),
    .b (alpha21 ),
    .c (alpha22 ),
    .d (alpha23 ),
    ///output
    .e (alpha_t2)
);

mod_max4 mod_max4_3
(
    ///input
    .a (alpha30 ),
    .b (alpha31 ),
    .c (alpha32 ),
    .d (alpha33 ),
    ///output
    .e (alpha_t3)
);

mod_max4 mod_max4_4
(
    ///input
    .a (alpha40 ),
    .b (alpha41 ),
    .c (alpha42 ),
    .d (alpha43 ),
    ///output
    .e (alpha_t4)
);

mod_max4 mod_max4_5
(
    ///input
    .a (alpha50 ),
    .b (alpha51 ),
    .c (alpha52 ),
    .d (alpha53 ),
    ///output
    .e (alpha_t5)
);

mod_max4 mod_max4_6
(
    ///input
    .a (alpha60 ),
    .b (alpha61 ),
    .c (alpha62 ),
    .d (alpha63 ),
    ///output
    .e (alpha_t6)
);

mod_max4 mod_max4_7
(
    ///input
    .a (alpha70 ),
    .b (alpha71 ),
    .c (alpha72 ),
    .d (alpha73 ),
    ///output
    .e (alpha_t7)
);

///alpha reg
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        { alpha7, alpha6, alpha5, alpha4,
            alpha3, alpha2, alpha1, alpha0 } <= 1'b0;
    end
    else begin
        if( clr_alpha )
            { alpha7, alpha6, alpha5, alpha4,
                alpha3, alpha2, alpha1, alpha0 } <= 1'b0;
        else if( alpha_source_val_d3 )
            { alpha7, alpha6, alpha5, alpha4,
                alpha3, alpha2, alpha1, alpha0 }
                <=
            { alpha_t7, alpha_t6, alpha_t5, alpha_t4,
                alpha_t3, alpha_t2, alpha_t1, alpha_t0 };
        else
            { alpha7, alpha6, alpha5, alpha4,
                alpha3, alpha2, alpha1, alpha0 }
                <=
            { alpha7, alpha6, alpha5, alpha4,
                alpha3, alpha2, alpha1, alpha0 };
    end
end


///*************************************************************************
///output
///*************************************************************************
 
///reg alpha_source_val_d1,alpha_source_val_d2;
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        {alpha_source_val_d4,alpha_source_val_d3,alpha_source_val_d2,alpha_source_val_d1} <= 3'b0;
    else
        {alpha_source_val_d4,alpha_source_val_d3,alpha_source_val_d2,alpha_source_val_d1}
            <= {alpha_source_val_d3,alpha_source_val_d2,alpha_source_val_d1,alpha_source_val};
end
 
assign  alpha = {alpha7,alpha6,alpha5,alpha4,alpha3,alpha2,alpha1,alpha0};
assign  alpha_sink_val = alpha_source_val_d4;

endmodule ///alpha_cal