alpha_cal.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : alpha_cal.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : alpha_cal
/// Called by    : max_log_map  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///               |----mod_max4_0
///               |----mod_max4_1
///               |----mod_max4_2
///               |----mod_max4_3
/// alpha_cal-----|----mod_max4_4
///               |----mod_max4_5
///               |----mod_max4_6
///               |----mod_max4_7
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-15  | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核alpha计算单元
///*********************************************************************

`timescale 1ns/100ps

module alpha_cal
    #(parameter SOFT_INFO_WIDTH  = 6'd6,                ///软信息宽度
                PRIOR_INFO_WIDTH = 6'd8,                ///先验信息宽度
                BRANCH_MATRIC_WIDTH = 6'd9,             ///分支度量数据宽度
                STATE_MATRIC_WIDTH = 6'd12  )           ///状态度量数据宽度
    (
    ///system i/f
    input              clk_sys,                         ///系统时钟信号
    input              rst_b,                           ///输入复位信号
    ///input i/f
    input      [SOFT_INFO_WIDTH*2-1:0]     ys,          ///soft info: system part
    input      [SOFT_INFO_WIDTH*2-1:0]     yp,          ///soft info: check part
    input      [PRIOR_INFO_WIDTH*3-1:0]    la,          ///prior info
    input                                  alpha_source_val,
    input                                  clr_alpha,   ///clr alpha and gamma reg
    ///output i/f
    output wire [STATE_MATRIC_WIDTH*8-1:0] alpha,
    output wire                            alpha_sink_val
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
reg                          alpha_source_val_d1;
reg                          alpha_source_val_d2;
reg                          alpha_source_val_d3;
reg                          alpha_source_val_d4;

reg [STATE_MATRIC_WIDTH-1:0] alpha7;
reg [STATE_MATRIC_WIDTH-1:0] alpha6;
reg [STATE_MATRIC_WIDTH-1:0] alpha5;
reg [STATE_MATRIC_WIDTH-1:0] alpha4;
reg [STATE_MATRIC_WIDTH-1:0] alpha3;
reg [STATE_MATRIC_WIDTH-1:0] alpha2;
reg [STATE_MATRIC_WIDTH-1:0] alpha1;
reg [STATE_MATRIC_WIDTH-1:0] alpha0;

///*********************************************************************
///主程序代码：
///*********************************************************************
reg [SOFT_INFO_WIDTH-1:0]  ys1,ys0,yp1,yp0;
reg [PRIOR_INFO_WIDTH-1:0] la3,la2,la1;

always @(posedge clk_sys) begin
    ys1 <= ys[SOFT_INFO_WIDTH*2-1:SOFT_INFO_WIDTH];
    ys0 <= ys[SOFT_INFO_WIDTH-1:0];

    yp1 <= yp[SOFT_INFO_WIDTH*2-1:SOFT_INFO_WIDTH];
    yp0 <= yp[SOFT_INFO_WIDTH-1:0];

    la3 <= la[PRIOR_INFO_WIDTH*3-1:PRIOR_INFO_WIDTH*2];
    la2 <= la[PRIOR_INFO_WIDTH*2-1:PRIOR_INFO_WIDTH];
    la1 <= la[PRIOR_INFO_WIDTH-1:0];
end

///*************************************************************************
///最高位扩展并延时一节拍
///*************************************************************************
reg [BRANCH_MATRIC_WIDTH-1:0] la3_d1,la2_d1,la1_d1;

always @( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        {la3_d1,la2_d1,la1_d1} <= 27'd0;
    end
    else begin
        la3_d1 <= {la3[PRIOR_INFO_WIDTH-1],la3};
        la2_d1 <= {la2[PRIOR_INFO_WIDTH-1],la2};
        la1_d1 <= {la1[PRIOR_INFO_WIDTH-1],la1};
    end
end

///*************************************************************************
///求取la1，la2，la3的最大并作最高位拓展
///*************************************************************************
wire [PRIOR_INFO_WIDTH-1:0]    la_max_a,la_max_b,la_max_c;
reg  [BRANCH_MATRIC_WIDTH-1:0] la_max;

assign la_max_a = la1 - la2;
assign la_max_b = la1 - la3;
assign la_max_c = la2 - la3;

always @( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        la_max <= 9'd0;
    else if(la1[7]==1'b1 & la2[7]==1'b1 & la3[7]==1'b1)
        la_max <= 9'd0;
    else
        case ({la_max_a[7], la_max_b[7], la_max_c[7]})
            3'b000,3'b001 : la_max <= {la1[PRIOR_INFO_WIDTH-1],la1};
            3'b100,3'b110 : la_max <= {la2[PRIOR_INFO_WIDTH-1],la2};
            default :       la_max <= {la3[PRIOR_INFO_WIDTH-1],la3};
        endcase
end

///*************************************************************************
///分支度量计算6，8，9
///*************************************************************************
reg [BRANCH_MATRIC_WIDTH-1:0] gamma15_t1,gamma14_t1,gamma13_t1,gamma12_t1,
                              gamma11_t1,gamma10_t1,gamma9_t1,gamma8_t1,
                              gamma7_t1,gamma6_t1,gamma5_t1,gamma4_t1,
                              gamma3_t1,gamma2_t1,gamma1_t1,gamma0_t1;

always @( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        gamma0_t1  <= 9'd0;
        gamma1_t1  <= 9'd0;
        gamma2_t1  <= 9'd0;
        gamma3_t1  <= 9'd0;
        gamma4_t1  <= 9'd0;
        gamma5_t1  <= 9'd0;
        gamma6_t1  <= 9'd0;
        gamma7_t1  <= 9'd0;
        gamma8_t1  <= 9'd0;
        gamma9_t1  <= 9'd0;
        gamma10_t1 <= 9'd0;
        gamma11_t1 <= 9'd0;
        gamma12_t1 <= 9'd0;
        gamma13_t1 <= 9'd0;
        gamma14_t1 <= 9'd0;
        gamma15_t1 <= 9'd0;
    end
    else begin
        gamma0_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma1_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma2_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma3_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma4_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma5_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma6_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma7_t1  <= + {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma8_t1  <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma9_t1  <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma10_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma11_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} + {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma12_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma13_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      + {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma14_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} + {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};

        gamma15_t1 <= - {{3{ys0[SOFT_INFO_WIDTH-1]}},ys0} - {{3{ys1[SOFT_INFO_WIDTH-1]}},ys1}
                      - {{3{yp0[SOFT_INFO_WIDTH-1]}},yp0} - {{3{yp1[SOFT_INFO_WIDTH-1]}},yp1};
    end
end

wire [BRANCH_MATRIC_WIDTH-1:0] gamma15_t2,gamma14_t2,gamma13_t2,gamma12_t2,
                               gamma11_t2,gamma10_t2,gamma9_t2, gamma8_t2,
                               gamma7_t2, gamma6_t2, gamma5_t2, gamma4_t2,
                               gamma3_t2, gamma2_t2, gamma1_t2, gamma0_t2;
///0-3
assign  gamma0_t2  = gamma0_t1 - la_max;
assign  gamma1_t2  = gamma1_t1 - la_max;
assign  gamma2_t2  = gamma2_t1 - la_max;
assign  gamma3_t2  = gamma3_t1 - la_max;
///4-7
assign  gamma4_t2  = gamma4_t1  + la1_d1 - la_max;
assign  gamma5_t2  = gamma5_t1  + la1_d1 - la_max;
assign  gamma6_t2  = gamma6_t1  + la1_d1 - la_max;
assign  gamma7_t2  = gamma7_t1  + la1_d1 - la_max;
///8-11
assign  gamma8_t2  = gamma8_t1  + la2_d1 - la_max;
assign  gamma9_t2  = gamma9_t1  + la2_d1 - la_max;
assign  gamma10_t2 = gamma10_t1 + la2_d1 - la_max;
assign  gamma11_t2 = gamma11_t1 + la2_d1 - la_max;
///12-15
assign  gamma12_t2 = gamma12_t1 + la3_d1 - la_max;
assign  gamma13_t2 = gamma13_t1 + la3_d1 - la_max;
assign  gamma14_t2 = gamma14_t1 + la3_d1 - la_max;
assign  gamma15_t2 = gamma15_t1 + la3_d1 - la_max;

///gamma reg