ctc_rx_arb.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_rx_arb.v
/// Author       : wangjinshan  yuanliuqing
/// Department   : 2nd IC department
/// Email        : [e-mail]
///
/// Module_name  : ctc_rx_arb
/// Called by    : ctc_rx_fsm  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// none
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-10  | 建立文件
///---------------------------------------------------------------------
/// 1.1-0       | 2006-10-09  | 更改为3个译码核
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC译码核输入仲裁
///*********************************************************************

`timescale 1ns/100ps

module ctc_rx_arb
    (
    ///interface signals with ctc_decoder_core1
    ///input
    input              core1_req,                   ///read request signal
    ///output
    output reg         core1_gnt,                   ///read grant signal

    ///interface signals with ctc_decoder_core2
    ///input
    input              core2_req,                   ///read request signal
    ///output
    output reg         core2_gnt,                   ///read grant signal

    ///interface signals with ctc_decoder_core3
    ///input
    input              core3_req,                   ///read request signal
    ///output
    output reg         core3_gnt,                   ///read grant signal

    ///interface signals with ctc_rx_fsm
    ///input
    input       [15:0] p_len,                       ///长度
    input              empty,                       ///pre_ctc_fifo空指示信号
    input              wr1_over,                    ///core1写完成信号
    input              wr2_over,                    ///core2写完成信号
    input              wr3_over,                    ///core3写完成信号

    ///interface with ctc_fifo1
    ///input
    input       [8:0]  ctc_fifo1_usedw,

    ///interface with ctc_fifo2
    ///input
    input       [8:0]  ctc_fifo2_usedw,

    ///interface with ctc_fifo3
    ///input
    input       [8:0]  ctc_fifo3_usedw,

     //system signals
    input              sys_clk,                     ///系统时钟信号
    input              reset_b                      ///输入复位信号
    );

///*********************************************************************
///local parameter define：(本地参数：)
///*********************************************************************
parameter       CTC_FIFO_THRESHOLD = 9'd340;        ///512-152=360 (152=4800-b/32+2)
parameter       IDLE               = 3'b001;
parameter       SEARCH             = 3'b010;
parameter       ST_WAIT            = 3'b100;

///*********************************************************************
///内部信号定义
///*********************************************************************
///internal signals
reg     [1:0]   current_point;                      ///current point for request
reg             schedule_succ;                      ///schedule is success
///reg             core_poll;                          ///轮循信号
/// State codes definitions:
reg     [2:0]   st_current;
reg     [2:0]   st_next;
reg             schedule_succ_next;
reg     [1:0]   current_point_next;

/// NextState logic (combinatorial)
/// The state machine (seperate the state machine from the output process)
/// State machine with separate computation processes
    always @(*) begin
        st_next = st_current;
        case(st_current)
            IDLE: 
                st_next = SEARCH;
            SEARCH:
                if(schedule_succ_next)
                    st_next = ST_WAIT;
                else
                    st_next = SEARCH;
            ST_WAIT:
                if(wr1_over | wr2_over | wr3_over)
                    st_next = SEARCH;
                else
                    st_next = ST_WAIT;
            default: st_next = IDLE;
        endcase
    end

    // Current State Logic (sequential)
    // state_intialization
    always @(posedge sys_clk or negedge reset_b) begin
        if(~reset_b)
            st_current <= IDLE;
        else
            st_current <= st_next;
    end  // state machine

    //output the schedule gnt
    reg    core1_gnt_next; //
    reg    core2_gnt_next; //
    reg    core3_gnt_next; //
    
    always @(*) begin
        // Set default values for outputs and signals
        core1_gnt_next = core1_gnt; //
        core2_gnt_next = core2_gnt; //
        core3_gnt_next = core3_gnt; //
        if(st_current==SEARCH && schedule_succ_next)
            case(current_point_next)
                2'b00: core1_gnt_next = 1'b1;
                2'b01: core2_gnt_next = 1'b1;
                2'b10: core3_gnt_next = 1'b1;
                default: begin
                    core1_gnt_next = core1_gnt; //
                    core2_gnt_next = core2_gnt; //
                    core3_gnt_next = core2_gnt; //
                end
            endcase
        else if(st_current==ST_WAIT && wr1_over)
            core1_gnt_next = 1'b0;
        else if(st_current==ST_WAIT && wr2_over)
            core2_gnt_next = 1'b0;
        else if(st_current==ST_WAIT && wr3_over)
            core3_gnt_next = 1'b0;
    end  //output the schedule gnt

    //Registered outputs logic
    always @(posedge sys_clk or negedge reset_b) begin
        if(~reset_b) begin
            core1_gnt <= 1'b0; //
            core2_gnt <= 1'b0; //
            core3_gnt <= 1'b0; //
        end 
        else begin 
            core1_gnt <= core1_gnt_next;
            core2_gnt <= core2_gnt_next;
            core3_gnt <= core3_gnt_next;
        end
    end   //Registered outputs

    //Schedule process
    always @(*) begin
        schedule_succ_next = schedule_succ;
        current_point_next = current_point;
        if(st_current==SEARCH) begin
            case (current_point)
                2'b00: 
                    if(~empty && core2_req && (ctc_fifo2_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b01;
                    end
                    else if(~empty && core3_req && (ctc_fifo3_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b10;
                    end
                    else if(~empty && core1_req && (ctc_fifo1_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b00;
                    end
                    else begin
                        schedule_succ_next = 1'b0;
                        current_point_next = 2'b00;
                    end                  
                
                2'b01: begin
                    if(~empty && core3_req && (ctc_fifo3_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b10;
                    end               
                    else   
                    if(~empty && core1_req && (ctc_fifo1_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b00;
                    end
                    else if(~empty && core2_req && (ctc_fifo2_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b01;
                    end   
                    else begin
                        schedule_succ_next = 1'b0;
                        current_point_next = 2'b01;
                    end
                end
                2'b10: begin
                    if(~empty && core1_req && (ctc_fifo1_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b00;
                    end
                    else if(~empty && core2_req && (ctc_fifo2_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b01;
                    end
                    else if(~empty && core3_req && (ctc_fifo3_usedw<CTC_FIFO_THRESHOLD)) begin
                        schedule_succ_next = 1'b1;
                        current_point_next = 2'b10;
                    end    
                    else begin
                        schedule_succ_next = 1'b0;
                        current_point_next = 2'b10;
                    end
                end     
                default: begin
                    schedule_succ_next = 1'b0;
                    current_point_next = 2'b00;
                end
            endcase
        end
    end   //arbiter schedule

      //Registered outputs logic
      always @ (posedge sys_clk or negedge reset_b) begin
          if(~reset_b) begin
              schedule_succ <= 1'b0;
              current_point <= 2'b00;
          end
          else begin
              schedule_succ <= schedule_succ_next;
              current_point <= current_point_next;
          end
      end //Registered outputs
                                               ///Registered outputs
endmodule  ///ctc_rx_arb