llr_max8.v

上传的是WIMAX系统中

//FILE_HEADER------------------------------------------------------------------
//Copyright: 2006 ZTE CORPORATION
//Company Confidential: This proprietary may be used only as authorized by a 
//                      agreement from WiMAX Department of ZTE CORPORATION.  
//----------------------------------------------------------------------------
//FILENAME       : llr_max8.v
//DEPARTMENT     : WiMAX department
//AUTHOR         : yuanliuqing
//AUTHOR'S EMAIL : [e-mail]
//----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION      DATE         AUTHOR       DESCRIPTION
// 0.1       2006-6-16     yuanliuqing   create
//---------------------------------------------------------------------------- 
//KEYWORDS       : max
//----------------------------------------------------------------------------
//PURPOSE        : select maximum number of 8 numbers, pure combinational logic.
//----------------------------------------------------------------------------
//PARAMETERS    
//PARAM NAME:        RANGE:            DESCRIPTION:        DEFAULT:   UNITS:
//
//----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy     : N/A
//Clock  Domains     : N/A
//Critical Timing    : N/A
//Test   Features    : N/A
//Asynchronous I/F   : N/A
//Scan Methodology   : Mux-D
//Instaniations      : N/A
//Synthesizable      : Yes
//Other              : N/A
//END_HEADER------------------------------------------------------------------

`timescale 1ns/100ps

module llr_max8
    (
        //system i/f
        clk_sys,
        rst_b,     
        //input i/f
        a,
        b,
        c,
        d,
        e,
        f,
        g,
        h,
        //output i/f
        z
    );
    //*************************************************************************
    parameter DATA_WIDTH = 6'd12;
    //*************************************************************************
    //ports direction
    //system i/f 
    input   clk_sys;        //system clock
    input   rst_b;          //reset signal, low valid    
    //input i/f
    input   [DATA_WIDTH-1:0]  a;
    input   [DATA_WIDTH-1:0]  b;
    input   [DATA_WIDTH-1:0]  c;
    input   [DATA_WIDTH-1:0]  d;
    input   [DATA_WIDTH-1:0]  e;
    input   [DATA_WIDTH-1:0]  f;
    input   [DATA_WIDTH-1:0]  g;
    input   [DATA_WIDTH-1:0]  h;    
    //output i/f
    output  [DATA_WIDTH-1:0]  z;
    //*************************************************************************
    //ports type
    //system i/f 
    wire    clk_sys;        //system clock
    wire    rst_b;          //reset signal, low valid 
    //input i/f
    wire    [DATA_WIDTH-1:0]  a;
    wire    [DATA_WIDTH-1:0]  b;
    wire    [DATA_WIDTH-1:0]  c;
    wire    [DATA_WIDTH-1:0]  d;
    wire    [DATA_WIDTH-1:0]  e;
    wire    [DATA_WIDTH-1:0]  f;
    wire    [DATA_WIDTH-1:0]  g;
    wire    [DATA_WIDTH-1:0]  h;
    //output i/f
    wire    [DATA_WIDTH-1:0]  z;
    //*************************************************************************

    wire    [DATA_WIDTH-1:0]  m;
    wire    [DATA_WIDTH-1:0]  n;
    
    wire    [DATA_WIDTH-1:0]  r;

    //************************************************************
    // all variables are signed
    // mod_max
    //************************************************************
        
    llr_max4 llr_max4_0
    (
        //system i/f    
        .clk_sys (clk_sys),
        .rst_b (rst_b),    
        //input signals
        .a  (a),
        .b  (b),
        .c  (c),
        .d  (d),
        //output signals
        .z  (m)
    );    

    llr_max4 llr_max4_1
    (
        //system i/f    
        .clk_sys (clk_sys),
        .rst_b (rst_b),    
        //input signals
        .a  (e),
        .b  (f),
        .c  (g),
        .d  (h),
        //output signals
        .z  (n)
    );  
    
//    assign r = m-n;
    sub12 sub12_u1
    (
    	.dataa   (m),
    	.datab   (n),
    	.result  (r)
	); 
	
   
	
    assign z = (!r[DATA_WIDTH-1])?m:n;
    
endmodule