output_packer.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : output_packer.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : output_packer
/// Called by    : ctc_decoder_datapath_top  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// output_packer-----|----hd_bit_ram
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-07-11  | 建立文件
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC译码核打包输出模块
///*********************************************************************

`timescale 1ns/100ps

module output_packer
    #(parameter WIN_SIZE            = 6'd32,        ///sliding window size, unit: lattice
                OUT_FIFO_DEPTH_WIDTH = 8'd9     )
    (
    ///system i/f
    input              clk_sys,                     ///系统时钟信号
    input              rst_b,                       ///输入复位信号
    ////hd i/f
    input       [1:0]  d,                           ///硬判决数据
    input              sop_sink,
    input              eop_sink,
    input              val_sink,
    ///packet para i/f
    input       [2:0]  packet_type,                 ///包类型
    input       [2:0]  packet_frame_end_flag,
    input       [1:0]  instance_num,                ///实例号
    input       [15:0] packet_length,               ///包长
    input       [2:0]  code_rate,                   ///码率
    input       [1:0]  modulate_type,               ///调制类型
    input       [15:0] burst_id,                    ///突发号
    input       [7:0]  fec_id,                      ///FEC号
    input       [4:0]  real_iter_no,                ///实际迭代次数
    input       [3:0]  segId,                       ///segment号
    ///iter_stop i/f
    input              iter_stop,                   ///迭代完成信号
    output wire        ready,                       ///空闲信号
    ///int/deint index i/f
    output wire        rd_int_ram,                  ///交织ram读信号
    input       [11:0] dat_rd_int_ram,              ///交织ram输出数据线
    output wire [11:0] adr_rd_int_ram,              ///交织ram读地址
    ///output i/f
    input   [OUT_FIFO_DEPTH_WIDTH-1'b1:0]       fifo_usedword,
    output reg  [31:0] dat_wr_fifo,                 ///FIFO输入数据线
    output reg         wr_fifo                      ///FIFO写信号
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
reg     [7:0]   rd_ram_counter;                     ///unit: 32-bit
wire            eff_adr_flag;
reg             eff_adr_flag_d1;

///input para buf
reg     [2:0]   packet_type_buf;
reg     [2:0]   packet_frame_end_flag_buf;
reg     [1:0]   instance_num_buf;
reg     [15:0]  packet_length_buf;
reg     [2:0]   code_rate_buf;
reg     [1:0]   modulate_type_buf;
reg     [15:0]  burst_id_buf;
reg     [7:0]   fec_id_buf;
reg     [4:0]   real_iter_no_buf;
reg     [3:0]   segId_buf;
reg     [15:0]  packet_length_32b;                  ///packet length 32-b

///*********************************************************************
///主程序代码：
///*********************************************************************
///buffer packet head parameters
    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b ) begin
            packet_type_buf           <= 3'd0;  //packet_type_buf <= 1'b0;   mahui 070704
            packet_frame_end_flag_buf <=3'd0;   //add by mahui 070704
            instance_num_buf          <= 2'd0;  //instance_num_buf <= 1'b0;  mahui 070704
            packet_length_buf         <= 16'd0; //packet_length_buf <= 1'b0; 
            code_rate_buf             <= 3'd0;  //code_rate_buf <= 1'b0;  
            modulate_type_buf         <= 2'd0;  //modulate_type_buf <= 1'b0;
            burst_id_buf              <= 16'd0; //burst_id_buf <= 1'b0;
            fec_id_buf                <= 8'd0;  //fec_id_buf <= 1'b0;
            real_iter_no_buf          <= 5'd0;  //real_iter_no_buf <= 1'b0;
            segId_buf                 <= 4'd0;  //add by mahui 070704
            packet_length_32b         <= 16'd0; //packet_length_32b <= 1'b0;
        end
        else begin
            if(iter_stop) begin
                packet_type_buf           <= packet_type;
                packet_frame_end_flag_buf <= packet_frame_end_flag; //add by mahui 070704
                instance_num_buf          <= instance_num;
                packet_length_buf         <= packet_length;
                code_rate_buf             <= code_rate;
                modulate_type_buf         <= modulate_type;
                burst_id_buf              <= burst_id;
                fec_id_buf                <= fec_id;
                real_iter_no_buf          <= real_iter_no;
                segId_buf                 <= segId;                 //add by mahui 070704
                packet_length_32b         <= (packet_length+8'd15)>>8'd4;
            end
            else begin
                packet_type_buf           <= packet_type_buf;
                packet_frame_end_flag_buf <= packet_frame_end_flag_buf;  //add by mahui 070704
                instance_num_buf          <= instance_num_buf;
                packet_length_buf         <= packet_length_buf;
                code_rate_buf             <= code_rate_buf;
                modulate_type_buf         <= modulate_type_buf;
                burst_id_buf              <= burst_id_buf;
                fec_id_buf                <= fec_id_buf;
                real_iter_no_buf          <= real_iter_no_buf;
                segId_buf                 <= segId_buf;         //add by mahui 070704
                packet_length_32b         <= packet_length_32b;
            end
        end
    end

wire   [OUT_FIFO_DEPTH_WIDTH:0]  fifo_empty_word_num;

///output fifo empty word num
assign  fifo_empty_word_num = (1'b1<<OUT_FIFO_DEPTH_WIDTH) -8'd10 - fifo_usedword;

///pack control fsm
reg     [4:0]   pack_state_current;
reg     [4:0]   pack_state_next;
///state definition for pack control fsm
parameter   READY       = 5'b00001,
            WAITING     = 5'b00010,
            OUT_HEAD0   = 5'b00100,
            OUT_HEAD1   = 5'b01000,
            OUT_DATA    = 5'b10000;

///pack control fsm
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        pack_state_current <= READY;
    else
        pack_state_current <= pack_state_next;
end


always @ ( * ) begin
    case( pack_state_current )
        READY:
        begin
            if(iter_stop)
            begin
                if( fifo_empty_word_num>=((packet_length+8'd15)>>8'd4) )
                    pack_state_next = OUT_HEAD0;
                else
                    pack_state_next = WAITING;
            end
            else
                pack_state_next = READY;
        end
        WAITING:
        begin
            if( fifo_empty_word_num>=packet_length_32b[9:0] )
                pack_state_next = OUT_HEAD0;
            else
                pack_state_next = WAITING;
        end
        OUT_HEAD0:
        begin
            pack_state_next = OUT_HEAD1;
        end
        OUT_HEAD1:
        begin
            pack_state_next = OUT_DATA;
        end
        OUT_DATA:
        begin
            if( rd_ram_counter>=packet_length_32b+1'b1 )
                pack_state_next = READY;
            else
                pack_state_next = OUT_DATA;
        end
        default:
        begin
            pack_state_next = READY;
        end
    endcase
end

assign  ready = (pack_state_current==READY);

///hd_bit_ram wr
reg             val_sink_d1;
reg     [1:0]   d_d1;
reg     [11:0]  wr_ram_counter;
reg     [7:0]   counter_mod_winsize;
reg             wr_ram;
reg     [1:0]   dat_wr_ram;
reg     [11:0]  adr_wr_ram;

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        val_sink_d1 <= 1'b0;
    else
        val_sink_d1 <= val_sink;
end

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        d_d1 <= 1'b0;
    else
        d_d1 <= d;
end

///generate hd_bit_ram wr signals concerned
///input val_sink is valid while pack control fsm is in READY state.
always @ ( * ) begin
    if( real_iter_no[0] )                           ///need deinterleaving
        wr_ram = (pack_state_current==READY) & (real_iter_no!=5'd0) & val_sink_d1 & eff_adr_flag_d1;
    else
        wr_ram = (pack_state_current==READY) & (real_iter_no!=5'd0) & val_sink & eff_adr_flag;
end

always @ ( * ) begin
    if( real_iter_no[0] )                           ///need deinterleaving
        adr_wr_ram = dat_rd_int_ram;
    else
        adr_wr_ram = wr_ram_counter;
end

///输入数据
always @ ( * ) begin
    if( real_iter_no[0] )                           ///need deinterleaving
    begin
        if( !wr_ram_counter[0] )
            dat_wr_ram = {d_d1[0],d_d1[1]};
        else
            dat_wr_ram = {d_d1[1],d_d1[0]};
    end
    else
    begin
        dat_wr_ram = {d[0],d[1]};
    end
end

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
    begin
        wr_ram_counter <= WIN_SIZE-1'd1;
        counter_mod_winsize <= WIN_SIZE-1'd1;
    end
    else
    begin
        if( pack_state_current==READY && eop_sink )
        begin
            wr_ram_counter <= WIN_SIZE-1'd1;
            counter_mod_winsize <= WIN_SIZE-1'd1;
        end
        else if( pack_state_current==READY && val_sink )
        begin
            if( counter_mod_winsize==8'd0 )
                wr_ram_counter <= wr_ram_counter+WIN_SIZE*2'd2-1'd1;
            else
                wr_ram_counter <= wr_ram_counter-1'd1;
            if( counter_mod_winsize==8'd0 )
                counter_mod_winsize <= WIN_SIZE-1'd1;
            else
                counter_mod_winsize <= counter_mod_winsize-1'd1;
        end
        else
        begin
            wr_ram_counter <= WIN_SIZE-1'd1;
            counter_mod_winsize <= WIN_SIZE-1'd1;
        end
    end
end

assign  eff_adr_flag = (wr_ram_counter<packet_length[11:0]);
assign  adr_rd_int_ram = eff_adr_flag ? wr_ram_counter:(wr_ram_counter-packet_length[11:0]);
assign  rd_int_ram = val_sink;

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        eff_adr_flag_d1 <= 1'b0;
    else
        eff_adr_flag_d1 <= eff_adr_flag;
end

///hd_bit_ram
wire    [7:0]   adr_rd_ram;
wire    [31:0]  dat_rd_ram;
reg             rd_en;
wire            rd_ram;
wire            dat_val;

///real_iter_no_buf[0]:
/// 1: the rd data of hd_bit_ram needn't perform deinterleaving operation.
/// 0: the rd data of hd_bit_ram need perform deinterleaving operation.

///instantiate hd_bit_ping_pong_ram
///dpram parameters: 2-b x 4096, no output register, single clock,
///                  wr_port_dat_width: 2-b      wr_port_adr_width: 12-b
///                  rd_port_dat_width: 32-b     rd_port_adr_width: 8-b
hd_bit_ram hd_bit_ram
    (
    .clock (clk_sys),
    .data (dat_wr_ram),
    .rdaddress (adr_rd_ram),
    .rden (rd_ram),
    .wraddress (adr_wr_ram),
    .wren (wr_ram),
    .q (dat_rd_ram)
    );

///hd_bit_ram rd
///generate hd_bit_ram rd signals concerned
assign  adr_rd_ram = rd_ram_counter;
assign  rd_ram = rd_en;

///读信号生成
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
    begin
        rd_en <= 1'b0;
    end
    else
    begin
        if( pack_state_current==OUT_DATA && rd_ram_counter<packet_length_32b-1'b1 )
        begin
            rd_en <= 1'b1;
        end
        else
        begin
            rd_en <= 1'b0;
        end
    end
end

reg             rd_en_d1;
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        rd_en_d1 <= 1'b0;
    else
        rd_en_d1 <= rd_en;
end

///RAM读计数器
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
    begin
        rd_ram_counter <= 1'b0;
    end
    else
    begin
        if( pack_state_current==OUT_DATA && (rd_en==1'b1 || rd_ram_counter!==1'b0) )
        begin
            rd_ram_counter <= rd_ram_counter + 1'b1;
        end
        else
        begin
            rd_ram_counter <= 1'b0;
        end
    end
end

assign dat_val = rd_en_d1;

///output sel: packet head or data
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        dat_wr_fifo <= 32'd0;
    else
    begin
        case( pack_state_current )
            OUT_HEAD0:
                            dat_wr_fifo <= {packet_type_buf,packet_frame_end_flag_buf,instance_num_buf,
                                            code_rate_buf,3'b000,modulate_type_buf,
                                            packet_length_buf>>2'd2};
            OUT_HEAD1:                              ///rev real_iter_no_buf[3:0] from [3:0] to [7:4]
                dat_wr_fifo <= {burst_id_buf,fec_id_buf,real_iter_no_buf[3:0],segId_buf};
            OUT_DATA:
            begin
                if( dat_val )
                    dat_wr_fifo <= dat_rd_ram;
                else
                    dat_wr_fifo <= 32'd0;
            end
            default:
                    dat_wr_fifo <= 32'd0;
        endcase
    end
end

///FIFO写信号生成
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        wr_fifo <= 1'b0;
    else
    begin
        case( pack_state_current )
            OUT_HEAD0:
                wr_fifo <= 1'b1;
            OUT_HEAD1:
                wr_fifo <= 1'b1;
            OUT_DATA:
                wr_fifo <= dat_val;
            default:
                wr_fifo <= 1'b0;
        endcase
    end
end
endmodule  ///output_packer