ctc_decoder_datapath_top.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_decoder_datapath_top.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : ctc_decoder_datapath_top
/// Called by    : ctc_decoder_core  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                              |----output_packer
///                              |----int_deint_adr_gen
/// ctc_decoder_datapath_top-----|----max_log_map
///                              |----stop_detect
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-07-03  | 建立文件
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC译码核数据处理顶层
///*********************************************************************

`timescale 1ns/100ps

module ctc_decoder_datapath_top
    #(parameter SOFT_INFO_WIDTH      = 6'd6,            ///软信息数据款度
                PRIOR_INFO_WIDTH     = 6'd8,            ///先验数据宽度
                LLR_INFO_WIDTH       = 6'd12,           ///对数似然比数据宽度
                OUT_FIFO_DEPTH_WIDTH = 8'd9     )       ///FIFO输出深度宽度
    (
    ///system i/f
    input              clk_sys,                         ///系统时钟信号
    input              rst_b,                           ///输入复位信号
    ///MAX-LOG-MAP input i/f
    input       [SOFT_INFO_WIDTH*2-1:0]    ys,          ///soft info: system part
    input       [SOFT_INFO_WIDTH*2-1:0]    yp,          ///soft info: check part
    input       [PRIOR_INFO_WIDTH*3-1:0]   la,          ///prior info
    input                                  sop_source,  ///start of source packet(not window)
    input                                  eop_source,  ///end of source packet(not window)
    input                                  val_source,  ///source data valid
    ///MAX-LOG-MAP output i/f
    output wire [PRIOR_INFO_WIDTH*3-1:0]   le,          ///output extrinsic info
    output wire                            sop_sink,    ///start of sink packet(not window)
    output wire                            eop_sink,    ///end of sink packet(not window)
    output wire                            val_sink,    ///sink data valid
    ///iter_stop i/f
    output wire                            iter_stop,   ///迭代停止信号
    ///packet para i/f
    input                           [2:0]  packet_type, ///包类型
    input                           [1:0]  instance_num,
    input                           [15:0] packet_length,
    input                           [2:0]  packet_frame_end_flag,
    input                           [2:0]  code_rate,
    input                           [1:0]  modulate_type,
    input                           [15:0] burst_id,
    input                           [7:0]  fec_id,
    input                           [3:0]  max_iter_no, ///最大迭代次数
    input                           [3:0]  segId, ///segment号
    ///output fifo i/f
    input   [OUT_FIFO_DEPTH_WIDTH-1'b1:0]  fifo_usedword,
    output wire                     [31:0] dat_wr_fifo, ///FIFO输入数据线
    output wire                            wr_fifo,     ///FIFO写信号
    ///int/deint adr gen i/f
    input                                  int_deint_adr_gen_en,    ///交织/解交织计算使能信号
    input                                  rd_int_ram0,             ///读交织地址ram信号
    input                           [11:0] adr_rd_int_ram0,         ///读交织地址ram地址
    output wire                     [11:0] dat_rd_int_ram0,         ///交织地址ram输出数据线
    input                                  rd_deint_ram0,           ///读解交织地址ram信号
    input                           [11:0] adr_rd_deint_ram0,       ///读解交织地址ram地址
    output wire                     [11:0] dat_rd_deint_ram0        ///解交织地址ram输出数据线
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
wire    [LLR_INFO_WIDTH*3-1:0]      l;                  ///output bit-pair llr
wire    [1:0]                       d;                  ///硬判决后数据输出

wire    [11:0]                      adr_rd_int_ram1;
wire    [11:0]                      dat_rd_int_ram1;
wire                                rd_int_ram1;

wire    [11:0]                      adr_rd_int_ram2;
wire    [11:0]                      dat_rd_int_ram2;
wire                                rd_int_ram2;

wire    [11:0]                      adr_rd_deint_ram1;
wire    [11:0]                      dat_rd_deint_ram1;
wire                                rd_deint_ram1;

wire    [4:0]                       real_iter_no;       ///实际迭代次数

max_log_map max_log_map
(
    //system i/f    
    .clk_sys        (clk_sys      ),   //ex i/f
    .rst_b          (rst_b        ),   //ex i/f
    //input i/f                   
    .ys             (ys           ),   //ex i/f
    .yp             (yp           ),   //ex i/f
    .la             (la           ),   //ex i/f
    .sop_source     (sop_source   ),   //ex i/f
    .eop_source     (eop_source   ),   //ex i/f
    .val_source     (val_source   ),   //ex i/f
    .packet_length  (packet_length),
    //output i/f
    .d              (d            ),
    .le             (le           ),   //ex i/f
    .l              (l            ),
    .sop_sink       (sop_sink     ),   //ex i/f
    .eop_sink       (eop_sink     ),   //ex i/f
    .val_sink       (val_sink     )    //ex i/f
);

int_deint_adr_gen int_deint_adr_gen
(
    //system i/f    
    .clk_sys              (clk_sys             ),   //ex i/f
    .rst_b                (rst_b               ),   //ex i/f
    //input i/f
    .int_deint_adr_gen_en (int_deint_adr_gen_en),   //ex i/f
    .packet_length        (packet_length       ),   //ex i/f
    //output i/f                               
    .rd_int_ram0          (rd_int_ram0         ),   //ex i/f
    .adr_rd_int_ram0      (adr_rd_int_ram0     ),   //ex i/f
    .dat_rd_int_ram0      (dat_rd_int_ram0     ),   //ex i/f
    .rd_int_ram1          (rd_int_ram1         ),   //time mux by stop_detect and output_packer module
    .adr_rd_int_ram1      (adr_rd_int_ram1     ),   //time mux by stop_detect and output_packer module
    .dat_rd_int_ram1      (dat_rd_int_ram1     ),   //time mux by stop_detect and output_packer module
    .rd_deint_ram0        (rd_deint_ram0       ),   //ex i/f
    .adr_rd_deint_ram0    (adr_rd_deint_ram0   ),   //ex i/f
    .dat_rd_deint_ram0    (dat_rd_deint_ram0   ),   //ex i/f
    .rd_deint_ram1        (rd_deint_ram1       ),
    .adr_rd_deint_ram1    (adr_rd_deint_ram1   ),
    .dat_rd_deint_ram1    (dat_rd_deint_ram1   )
);

assign dat_rd_int_ram2 = dat_rd_int_ram1;



stop_detect stop_detect
(
    //system i/f    
    .clk_sys           (clk_sys          ),  //ex i/f
    .rst_b             (rst_b            ),  //ex i/f
    //max-log-map i/f                    
    .d                 (d                ),
    .le                (le               ),
    .l                 (l                ),
    .sop_sink          (sop_sink         ),
    .eop_sink          (eop_sink         ),
    .val_sink          (val_sink         ), 
    //packet para i/f
    .packet_length     (packet_length    ),  //ex i/f
    .code_rate         (code_rate        ),  //ex i/f
    .modulate_type     (modulate_type    ),  //ex i/f
    .max_iter_no       (max_iter_no      ),  //ex i/f
    .real_iter_no      (real_iter_no     ),  //ex i/f
    //iter_stop i/f
    .iter_stop         (iter_stop        ),  //ex i/f
    //int/deint index i/f                
    .rd_int_ram        (rd_int_ram1      ),
    .adr_rd_int_ram    (adr_rd_int_ram1  ),
    .dat_rd_int_ram    (dat_rd_int_ram1  ),
    .rd_deint_ram      (rd_deint_ram1    ),
    .adr_rd_deint_ram  (adr_rd_deint_ram1),
    .dat_rd_deint_ram  (dat_rd_deint_ram1)
);

output_packer output_packer
(
    //system i/f    
    .clk_sys              (clk_sys              ), //ex i/f
    .rst_b                (rst_b                ), //ex i/f
    //hd i/f                                    
    .d                    (d                    ),
    .sop_sink             (sop_sink             ),
    .eop_sink             (eop_sink             ),
    .val_sink             (val_sink             ),
    //packet para i/f
    .packet_type          (packet_type          ), //ex i/f
    .packet_frame_end_flag(packet_frame_end_flag), //add by mahui 070704
    .instance_num         (instance_num         ), //ex i/f
    .packet_length        (packet_length        ), //ex i/f
    .code_rate            (code_rate            ), //ex i/f
    .modulate_type        (modulate_type        ), //ex i/f
    .burst_id             (burst_id             ), //ex i/f
    .fec_id               (fec_id               ), //ex i/f
    .real_iter_no         (real_iter_no         ),
    .segId                (segId                ), //Segment ID  add by mahui 070704
    //iter_stop i/f
    .iter_stop            (iter_stop            ),
    .ready                (                     ),
    //int/deint index i/f                       
    .rd_int_ram           (rd_int_ram2          ),
    .adr_rd_int_ram       (adr_rd_int_ram2      ),
    .dat_rd_int_ram       (dat_rd_int_ram2      ),
    //output i/f
    .fifo_usedword        (fifo_usedword        ), //ex i/f
    .dat_wr_fifo          (dat_wr_fifo          ), //ex i/f
    .wr_fifo              (wr_fifo              )  //ex i/f
);
endmodule  ///ctc_decoder_datapath_top