ctc_decoder.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_decoder.v
/// Author       : wangjinshan         yuanliuqing
/// Department   : 2nd IC department
/// Email        : [e-mail]
///
/// Module_name  : ctc_decoder
/// Called by    : ctc_path_top  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                 |----ctc_dpram_11
///                 |----ctc_dpram_12
///                 |----ctc_dpram_21
///                 |----ctc_dpram_22
///                 |----ctc_dpram_31
///                 |----ctc_dpram_32
/// ctc_decoder-----|----ctc_rx_fsm
///                 |----ctc_tx_fsm
///                 |----ctc_fifo1
///                 |----ctc_fifo2
///                 |----ctc_fifo3
///                 |----ctc_decoder_core1
///                 |----ctc_decoder_core2
///                 |----ctc_decoder_core3
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-05-20  | 建立文件
///---------------------------------------------------------------------
/// 1.1-0       | 2006-10-09  | 更改为3个译码核
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码器顶层文件，包含3个译码核。
///*********************************************************************

`timescale 1ns/100ps

module ctc_decoder
    (
    //system signals
    input              sys_clk,                     ///系统时钟信号
    input              reset_b,                     ///输入复位信号

    //pre_ctc_fifo i/f
    input              empty_pre_ctc_fifo,          ///输入FIFO空信号
    input       [12:0] usedw_pre_ctc_fifo,          ///输入FIFO写使用信号
    output wire        rd_pre_ctc_fifo,             ///输入FIFO读信号
    input              eop_rd_pre_ctc_fifo,         ///输入FIFO包结束信号
    input       [31:0] dat_rd_pre_ctc_fifo,         ///输入FIFO写数据线

    //post_ctc_fifo i/f
    input              full_post_ctc_fifo,          ///输出FIFO满信号
    input              empty_post_ctc_fifo,         ///输出FIFO空信号
    output wire        wr_post_ctc_fifo,            ///输出FIFO写信号
    output wire        eop_wr_post_ctc_fifo,        ///输出FIFO包结束信号
    output wire [31:0] dat_wr_post_ctc_fifo,        ///输出FIFO写数据线
    input       [8:0]  wrusedword_post_ctc_fifo     ///输出FIFO写使用信号
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
///internal signal
///ctc_dpram_11
wire    [23:0]  dpram11_wrdat;                      ///dpram写数据线
wire            dpram11_wr;                         ///dpram写信号
wire    [10:0]  dpram11_wradr;                      ///dpram写地址
wire            dpram11_rd;                         ///dpram读信号
wire    [11:0]  dpram11_rdadr;                      ///dpram读地址
wire    [11:0]  dpram11_rddat;                      ///dpram读数据线

//ctc_dpram_12
wire    [47:0]  dpram12_wrdat;
wire            dpram12_wr;
wire    [10:0]  dpram12_wradr;
wire            dpram12_rd;
wire    [11:0]  dpram12_rdadr;
wire    [23:0]  dpram12_rddat;

//ctc_dpram_21
wire    [23:0]  dpram21_wrdat;
wire            dpram21_wr;
wire    [10:0]  dpram21_wradr;
wire            dpram21_rd;
wire    [11:0]  dpram21_rdadr;
wire    [11:0]  dpram21_rddat;

//ctc_dpram_22
wire    [47:0]  dpram22_wrdat;
wire            dpram22_wr;
wire    [10:0]  dpram22_wradr;
wire            dpram22_rd;
wire    [11:0]  dpram22_rdadr;
wire    [23:0]  dpram22_rddat;

//ctc_dpram_31
wire    [23:0]  dpram31_wrdat;
wire            dpram31_wr;
wire    [10:0]  dpram31_wradr;
wire            dpram31_rd;
wire    [11:0]  dpram31_rdadr;
wire    [11:0]  dpram31_rddat;

//ctc_dpram_32
wire    [47:0]  dpram32_wrdat;
wire            dpram32_wr;
wire    [10:0]  dpram32_wradr;
wire            dpram32_rd;
wire    [11:0]  dpram32_rdadr;
wire    [23:0]  dpram32_rddat;

wire            ctc_fifo1_full;                     ///译码结果输出FIFO满信号
wire            ctc_fifo1_empty;                    ///译码结果输出FIFO空信号
wire            ctc_fifo1_rdreq;                    ///译码结果输出FIFO读信号
wire    [31:0]  ctc_fifo1_rddat;                    ///译码结果输出FIFO数据线
wire            ctc_fifo1_wrreq;                    ///译码结果输出FIFO写信号
wire    [31:0]  ctc_fifo1_wrdat;                    ///译码结果输出FIFO数据线
wire    [8:0]   ctc_fifo1_usedw;                    ///译码结果输出FIFO空间使用数

wire            ctc_fifo2_full;
wire            ctc_fifo2_empty;
wire            ctc_fifo2_rdreq;
wire    [31:0]  ctc_fifo2_rddat;
wire            ctc_fifo2_wrreq;
wire    [31:0]  ctc_fifo2_wrdat;
wire    [8:0]   ctc_fifo2_usedw;

wire            ctc_fifo3_full;
wire            ctc_fifo3_empty;
wire            ctc_fifo3_rdreq;
wire    [31:0]  ctc_fifo3_rddat;
wire            ctc_fifo3_wrreq;
wire    [31:0]  ctc_fifo3_wrdat;
wire    [8:0]   ctc_fifo3_usedw;

wire            core1_req;                          ///应答信号
wire            core1_gnt;                          ///请求信号
wire    [15:0]  rx2ctrl1_length;                    ///FEC译码块的长度
wire    [2:0]   rx2ctrl1_type;                      ///类型号
wire    [1:0]   rx2ctrl1_inst;                      ///instance
wire    [2:0]   rx2ctrl1_code_rate;                 ///码率 000:HARQ 001:1/2 010:2/3 011:3/4
wire    [1:0]   rx2ctrl1_modu_type;                 ///00为QPSK，01为16QAM，10为64QAM
wire    [15:0]  rx2ctrl1_bnum;                      ///突发号
wire    [7:0]   rx2ctrl1_fnum;                      //FEC号
wire    [3:0]   rx2ctrl1_miter;                     ///最大迭代次数
wire    [3:0]   rx2ctrl1_segId;                     ///add by mahui 070704
wire            core2_req;
wire            core2_gnt;
wire    [15:0]  rx2ctrl2_length;
wire    [2:0]   rx2ctrl2_type;
wire    [1:0]   rx2ctrl2_inst;
wire    [2:0]   rx2ctrl2_code_rate;
wire    [1:0]   rx2ctrl2_modu_type;
wire    [15:0]  rx2ctrl2_bnum;
wire    [7:0]   rx2ctrl2_fnum;
wire    [3:0]   rx2ctrl2_miter;
wire    [3:0]   rx2ctrl2_segId;                     ///add by mahui 070704
wire            core3_req;
wire            core3_gnt;
wire    [15:0]  rx2ctrl3_length;
wire    [2:0]   rx2ctrl3_type;
wire    [1:0]   rx2ctrl3_inst;
wire    [2:0]   rx2ctrl3_code_rate;
wire    [1:0]   rx2ctrl3_modu_type;
wire    [15:0]  rx2ctrl3_bnum;
wire    [7:0]   rx2ctrl3_fnum;
wire    [3:0]   rx2ctrl3_miter;
wire    [3:0]   rx2ctrl3_segId;                     ///add by mahui 070704
wire            wr1_over;                           ///数据输入完成
wire            wr2_over;
wire            wr3_over;
wire            dec1_finish;                        ///译码迭代完成
wire            dec2_finish;
wire            dec3_finish;

wire    [2:0]   rx2ctrl1_frame_end_flag;  //帧结束标志    //add by mahui 070704
wire    [2:0]   rx2ctrl2_frame_end_flag;  //帧结束标志    //add by mahui 070704
wire    [2:0]   rx2ctrl3_frame_end_flag;  //帧结束标志    //add by mahui 070704


///*********************************************************************
///主程序代码：
///*********************************************************************
///ctc decoder core1 ram: AB, direct/int
ctc_dpram_1  ctc_dpram_11
    (
    .clock     ( sys_clk ),
    .data      ( dpram11_wrdat[23:0] ),
    .rdaddress ( dpram11_rdadr ),
    .rden      ( dpram11_rd ),
    .wraddress ( dpram11_wradr ),
    .wren      ( dpram11_wr ),
    .q         ( dpram11_rddat[11:0] )
    );

///Y1Y2W1W2, direct
ctc_dpram_2  ctc_dpram_12
    (
    .clock     ( sys_clk ),
    .data      ( dpram12_wrdat[47:0] ),
    .rdaddress ( dpram12_rdadr ),
    .rden      ( dpram12_rd ),
    .wraddress ( dpram12_wradr ),
    .wren      ( dpram12_wr ),
    .q         ( dpram12_rddat[23:0] )
    );

///ctc decoder core2 ram: AB, direct/int
ctc_dpram_1  ctc_dpram_21
    (
    .clock     ( sys_clk ),
    .data      ( dpram21_wrdat[23:0] ),
    .rdaddress ( dpram21_rdadr ),
    .rden      ( dpram21_rd ),
    .wraddress ( dpram21_wradr ),
    .wren      ( dpram21_wr ),
    .q         ( dpram21_rddat[11:0] )
    );

///Y1Y2W1W2, direct
ctc_dpram_2  ctc_dpram_22
    (
    .clock     ( sys_clk ),
    .data      ( dpram22_wrdat[47:0] ),
    .rdaddress ( dpram22_rdadr ),
    .rden      ( dpram22_rd ),
    .wraddress ( dpram22_wradr ),
    .wren      ( dpram22_wr ),
    .q         ( dpram22_rddat[23:0] )
    );

///ctc decoder core3 ram: AB, direct/int
ctc_dpram_1  ctc_dpram_31
    (
    .clock     ( sys_clk ),
    .data      ( dpram31_wrdat[23:0] ),
    .rdaddress ( dpram31_rdadr ),
    .rden      ( dpram31_rd ),
    .wraddress ( dpram31_wradr ),
    .wren      ( dpram31_wr ),
    .q         ( dpram31_rddat[11:0] )
    );

///Y1Y2W1W2, direct
ctc_dpram_2  ctc_dpram_32
    (
    .clock     ( sys_clk ),
    .data      ( dpram32_wrdat[47:0] ),
    .rdaddress ( dpram32_rdadr ),