l_le_hd_cal.v

上传的是WIMAX系统中

            lt27 <= lt27;
            lt26 <= lt26;
            lt25 <= lt25;
            lt24 <= lt24;
            lt23 <= lt23;
            lt22 <= lt22;
            lt21 <= lt21;
            lt20 <= lt20;

            lt17 <= lt17;
            lt16 <= lt16;
            lt15 <= lt15;
            lt14 <= lt14;
            lt13 <= lt13;
            lt12 <= lt12;
            lt11 <= lt11;
            lt10 <= lt10;

            lt07 <= lt07;
            lt06 <= lt06;
            lt05 <= lt05;
            lt04 <= lt04;
            lt03 <= lt03;
            lt02 <= lt02;
            lt01 <= lt01;
            lt00 <= lt00;
        end
    end
end

//pipeline depth: 1cycle
llr_max8 llr_max8_3
(
    //system i/f
    .clk_sys (clk_sys),
    .rst_b   (rst_b  ),
    //input signals
    .a       (lt37   ),
    .b       (lt36   ),
    .c       (lt35   ),
    .d       (lt34   ),
    .e       (lt33   ),
    .f       (lt32   ),
    .g       (lt31   ),
    .h       (lt30   ),
    //output signals
    .z       (lt3    )
);

//pipeline depth: 1cycle
llr_max8 llr_max8_2
(
    //system i/f
    .clk_sys (clk_sys),
    .rst_b   (rst_b  ),
    //input signals
    .a       (lt27   ),
    .b       (lt26   ),
    .c       (lt25   ),
    .d       (lt24   ),
    .e       (lt23   ),
    .f       (lt22   ),
    .g       (lt21   ),
    .h       (lt20   ),
    //output signals
    .z       (lt2    )
);

//pipeline depth: 1cycle
llr_max8 llr_max8_1
(
    //system i/f
    .clk_sys (clk_sys),
    .rst_b   (rst_b  ),
    //input signals
    .a       (lt17   ),
    .b       (lt16   ),
    .c       (lt15   ),
    .d       (lt14   ),
    .e       (lt13   ),
    .f       (lt12   ),
    .g       (lt11   ),
    .h       (lt10   ),
    //output signals
    .z       (lt1    )
);

//pipeline depth: 1cycle
llr_max8 llr_max8_0
(
    //system i/f
    .clk_sys (clk_sys),
    .rst_b   (rst_b  ),
    //input signals
    .a       (lt07   ),
    .b       (lt06   ),
    .c       (lt05   ),
    .d       (lt04   ),
    .e       (lt03   ),
    .f       (lt02   ),
    .g       (lt01   ),
    .h       (lt00   ),
    //output signals
    .z       (lt0    )
);

//cal l
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        l3 <= 1'b0;
        l2 <= 1'b0;
        l1 <= 1'b0;
    end
    else if( l_source_val_d3 ) begin    //fyz修改
        l3 <= lt3-lt0;
        l2 <= lt2-lt0;
        l1 <= lt1-lt0;
    end
    else begin
        l3 <= l3;
        l2 <= l2;
        l1 <= l1;
    end
end

always @( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        {l3_d2,l2_d2,l1_d2} <= 1'b0;
        {l3_d1,l2_d1,l1_d1} <= 1'b0;
    end
    else begin
        {l3_d2,l2_d2,l1_d2} <= {l3_d1,l2_d1,l1_d1};
        {l3_d1,l2_d1,l1_d1} <= {l3,l2,l1};
    end
end


//*************************************************************************
//cal le
//*************************************************************************

//cal lc
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        {lc3,lc2,lc1} <= 1'b0;
    else begin
        lc3 <= -( {ys1[SOFT_INFO_WIDTH-1],ys1,1'b0} + {ys0[SOFT_INFO_WIDTH-1],ys0,1'b0} );
        lc2 <= -( {ys0[SOFT_INFO_WIDTH-1],ys0,1'b0} );
        lc1 <= -( {ys1[SOFT_INFO_WIDTH-1],ys1,1'b0} );
    end
end

always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        {lc3_d1,lc2_d1,lc1_d1} <= 24'd0;
        {lc3_d2,lc2_d2,lc1_d2} <= 24'd0;
    end
    else begin
        {lc3_d1,lc2_d1,lc1_d1} <= {lc3,lc2,lc1};
        {lc3_d2,lc2_d2,lc1_d2} <= {lc3_d1,lc2_d1,lc1_d1};
    end
end

assign  la3 = la[PRIOR_INFO_WIDTH*3-1:PRIOR_INFO_WIDTH*2];
assign  la2 = la[PRIOR_INFO_WIDTH*2-1:PRIOR_INFO_WIDTH*1];
assign  la1 = la[PRIOR_INFO_WIDTH*1-1:PRIOR_INFO_WIDTH*0];

always @( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b ) begin
        {la3_d1,la2_d1,la1_d1} <= 24'd0;
        {la3_d2,la2_d2,la1_d2} <= 24'd0;
        {la3_d3,la2_d3,la1_d3} <= 24'd0;
    end
    else begin
        {la3_d1,la2_d1,la1_d1} <= {la3,la2,la1};
        {la3_d2,la2_d2,la1_d2} <= {la3_d1,la2_d1,la1_d1};
        {la3_d3,la2_d3,la1_d3} <= {la3_d2,la2_d2,la1_d2};
    end
end

///////////////////////////////////////////////////////////////////////////////////////////////////
reg    [LE_CAL_WIDTH-1:0]   pre_tmp_le3,pre_tmp_le2,pre_tmp_le1;
always @(posedge clk_sys or negedge rst_b) begin
    if(!rst_b) begin
        pre_tmp_le3 <= 1'b0;
        pre_tmp_le2 <= 1'b0;
        pre_tmp_le1 <= 1'b0;
    end
    else begin
        pre_tmp_le3 <= {{7{lc3_d2[LC_WIDTH-1]}},lc3_d2} + {{7{la3_d3[PRIOR_INFO_WIDTH-1]}},la3_d3};
        pre_tmp_le2 <= {{7{lc2_d2[LC_WIDTH-1]}},lc2_d2} + {{7{la2_d3[PRIOR_INFO_WIDTH-1]}},la2_d3};
        pre_tmp_le1 <= {{7{lc1_d2[LC_WIDTH-1]}},lc1_d2} + {{7{la1_d3[PRIOR_INFO_WIDTH-1]}},la1_d3};
    end
end
assign pre_norm_le3 = {{3{l3[LLR_INFO_WIDTH-1]}},l3} - pre_tmp_le3;
assign pre_norm_le2 = {{3{l2[LLR_INFO_WIDTH-1]}},l2} - pre_tmp_le2;
assign pre_norm_le1 = {{3{l1[LLR_INFO_WIDTH-1]}},l1} - pre_tmp_le1;


//mul by 0.75(3/4), arithmatic shift

//mul 3
assign pre_satu_tmp_le3 = ((pre_norm_le3<<1'b1)+pre_norm_le3);
assign pre_satu_tmp_le2 = ((pre_norm_le2<<1'b1)+pre_norm_le2);
assign pre_satu_tmp_le1 = ((pre_norm_le1<<1'b1)+pre_norm_le1);
//div 4
assign pre_satu_le3 = {{2{pre_satu_tmp_le3[LE_CAL_WIDTH-1]}},pre_satu_tmp_le3[LE_CAL_WIDTH-1:2]};
assign pre_satu_le2 = {{2{pre_satu_tmp_le2[LE_CAL_WIDTH-1]}},pre_satu_tmp_le2[LE_CAL_WIDTH-1:2]};
assign pre_satu_le1 = {{2{pre_satu_tmp_le1[LE_CAL_WIDTH-1]}},pre_satu_tmp_le1[LE_CAL_WIDTH-1:2]};

always @( posedge clk_sys )
    if(pre_norm_le3>15'hAA && !pre_norm_le3[LE_CAL_WIDTH-1])
        pre_le3 <= 8'd127;
    else if(pre_norm_le3<15'h7F55 && pre_norm_le3[LE_CAL_WIDTH-1])
        pre_le3 <= -8'd128;
    else
        pre_le3 <= pre_satu_le3[7:0];
always @( posedge clk_sys )
    if(pre_norm_le2>15'hAA && !pre_norm_le2[LE_CAL_WIDTH-1])
        pre_le2 <= 8'd127;
    else if(pre_norm_le2<15'h7F55 && pre_norm_le2[LE_CAL_WIDTH-1])
        pre_le2 <= -8'd128;
    else
        pre_le2 <= pre_satu_le2[7:0];
always @( posedge clk_sys )
    if(pre_norm_le1>15'hAA && !pre_norm_le1[LE_CAL_WIDTH-1])
        pre_le1 <= 8'd127;
    else if(pre_norm_le1<15'h7F55 && pre_norm_le1[LE_CAL_WIDTH-1])
        pre_le1 <= -8'd128;
    else
        pre_le1 <= pre_satu_le1[7:0];

always @( posedge clk_sys or negedge rst_b )  begin
    if( !rst_b ) begin
        le3 <= 1'b0;
        le2 <= 1'b0;
        le1 <= 1'b0;
    end
    else begin
        if( l_source_val_d5 ) begin
            le3 <= pre_le3;
            le2 <= pre_le2;
            le1 <= pre_le1;
        end
        else begin
            le3 <= le3;
            le2 <= le2;
            le1 <= le1;
        end
    end
end

//*************************************************************************
//cal hard-decision
//*************************************************************************

reg  [LLR_INFO_WIDTH-1:0]  hd_tmp1,hd_tmp2,hd_tmp3;

always @(posedge clk_sys or negedge rst_b) begin
    if(!rst_b) begin
        hd_tmp1 <= 1'b0;
        hd_tmp2 <= 1'b0;
        hd_tmp3 <= 1'b0;
    end
    else begin
        hd_tmp1 <= l1 - l2;
        hd_tmp2 <= l1 - l3;
        hd_tmp3 <= l2 - l3;
    end
end

always @ ( posedge clk_sys or negedge rst_b )
    if ( !rst_b )
        d_hd <= 2'b00;
    else if ( l1_d1[LLR_INFO_WIDTH-1] & l2_d1[LLR_INFO_WIDTH-1] & l3_d1[LLR_INFO_WIDTH-1])
        d_hd <= 2'b00;
    else
        case ({hd_tmp1[LLR_INFO_WIDTH-1],hd_tmp2[LLR_INFO_WIDTH-1],hd_tmp3[LLR_INFO_WIDTH-1]})
            3'b001,3'b000: d_hd <= 2'b01;
            3'b100,3'b110: d_hd <= 2'b10;
            3'b011,3'b111: d_hd <= 2'b11;
            default      : d_hd <= 2'b00;
        endcase

//*************************************************************************
//output
//*************************************************************************

//reg l_source_val_d1,l_source_val_d2,l_source_val_d3;
always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            {l_source_val_d6,l_source_val_d5,l_source_val_d4,l_source_val_d3,l_source_val_d2,l_source_val_d1} <= 1'b0;
        else
            {l_source_val_d6,l_source_val_d5,l_source_val_d4,l_source_val_d3,l_source_val_d2,l_source_val_d1}
                <= {l_source_val_d5,l_source_val_d4,l_source_val_d3,l_source_val_d2,l_source_val_d1,l_source_val};
    end
assign   l_sink_val = l_source_val_d6;

assign d  = d_hd;
assign le = {le3,le2,le1};
assign l  = {l3_d2,l2_d2,l1_d2};

endmodule