📄 l_le_hd_cal.v
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///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name : l_le_hd_cal.v
/// Author : yuanliuqing
/// Department : WiMAX department
/// Email : yuan.liuqing@zte.com.cn
///
/// Module_name : l_le_hd_cal
/// Called by : max_log_map module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// |----llr_max8_3
/// |----llr_max8_2
/// l_le_hd_cal-----|----llr_max8_1
/// |----llr_max8_0
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version | Date | Author Description
///---------------------------------------------------------------------
/// 1.0-0 | 2006-06-15 | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核le计算单元
///*********************************************************************
`timescale 1ns/100ps
module l_le_hd_cal
#(parameter SOFT_INFO_WIDTH = 6'd6, ///软信息数据宽度
PRIOR_INFO_WIDTH = 6'd8, ///先验信息数据宽度
BRANCH_MATRIC_WIDTH = 6'd9, ///分支度量数据宽度
STATE_MATRIC_WIDTH = 6'd12, ///状态度量数据宽度
LLR_INFO_WIDTH = 6'd12, ///alpha + gamma + beta
LC_WIDTH = 6'd8, ///后验对数似然比
LE_CAL_WIDTH = 6'd15 ) ///对数似然比数据宽度
(
///system i/f
input clk_sys, ///系统时钟信号
input rst_b, ///输入复位信号
///input i/f
input [STATE_MATRIC_WIDTH*8-1:0] alpha, ///alpha
input [STATE_MATRIC_WIDTH*8-1:0] beta, ///beta
input [BRANCH_MATRIC_WIDTH*16-1:0] gamma, ///gamma
input [SOFT_INFO_WIDTH*2-1:0] ys, ///soft info: system part
input [PRIOR_INFO_WIDTH*3-1:0] la, ///prior info
input l_source_val,
input clr_l, ///clr alpha and gamma reg
///output i/f
output wire [1:0] d, ///dual-binary hard-decision
output wire [PRIOR_INFO_WIDTH*3-1:0] le, ///extrinsic info
output wire [LLR_INFO_WIDTH*3-1:0] l, ///dual-binary LLR
output l_sink_val
);
///*********************************************************************
///内部信号定义
///*********************************************************************
wire [SOFT_INFO_WIDTH-1:0] ys0,ys1;
wire [STATE_MATRIC_WIDTH-1:0] alpha7,alpha6,alpha5,alpha4, //alpha
alpha3,alpha2,alpha1,alpha0;
///fyz增加
reg [STATE_MATRIC_WIDTH-1:0] alpha7_d,alpha6_d,alpha5_d,alpha4_d,
alpha3_d,alpha2_d,alpha1_d,alpha0_d;
wire [STATE_MATRIC_WIDTH-1:0] beta7,beta6,beta5,beta4, //beta
beta3,beta2,beta1,beta0;
wire [BRANCH_MATRIC_WIDTH-1:0] gamma15,gamma14,gamma13,gamma12,//gamma
gamma11,gamma10,gamma9,gamma8,
gamma7,gamma6,gamma5,gamma4,
gamma3,gamma2,gamma1,gamma0;
reg l_source_val_d1,
l_source_val_d2,
l_source_val_d3,
l_source_val_d4,
l_source_val_d5,
l_source_val_d6;
//l
reg [LLR_INFO_WIDTH-1:0] lt37,lt36,lt35,lt34,lt33,lt32,lt31,lt30,
lt27,lt26,lt25,lt24,lt23,lt22,lt21,lt20,
lt17,lt16,lt15,lt14,lt13,lt12,lt11,lt10,
lt07,lt06,lt05,lt04,lt03,lt02,lt01,lt00;
wire [LLR_INFO_WIDTH-1:0] lt3,lt2,lt1,lt0;
reg [LLR_INFO_WIDTH-1:0] l3,l2,l1;
///fyz增加
reg [LLR_INFO_WIDTH-1:0] lt37_tmp,lt36_tmp,lt35_tmp,lt34_tmp,lt33_tmp,lt32_tmp,lt31_tmp,lt30_tmp,
lt27_tmp,lt26_tmp,lt25_tmp,lt24_tmp,lt23_tmp,lt22_tmp,lt21_tmp,lt20_tmp,
lt17_tmp,lt16_tmp,lt15_tmp,lt14_tmp,lt13_tmp,lt12_tmp,lt11_tmp,lt10_tmp,
lt07_tmp,lt06_tmp,lt05_tmp,lt04_tmp,lt03_tmp,lt02_tmp,lt01_tmp,lt00_tmp;
//cal le
wire [LE_CAL_WIDTH-1:0] pre_norm_le3,pre_norm_le2,pre_norm_le1;
wire [LE_CAL_WIDTH-1:0] pre_satu_tmp_le3,pre_satu_tmp_le2,pre_satu_tmp_le1;
wire [LE_CAL_WIDTH-1:0] pre_satu_le3,pre_satu_le2,pre_satu_le1;
reg [PRIOR_INFO_WIDTH-1:0] pre_le3,pre_le2,pre_le1;
reg [PRIOR_INFO_WIDTH-1:0] le3,le2,le1;
//delays l 1 cycles
reg [LLR_INFO_WIDTH-1:0] l3_d1,l2_d1,l1_d1;
reg [LLR_INFO_WIDTH-1:0] l3_d2,l2_d2,l1_d2;
//cal lc
reg [LC_WIDTH-1:0] lc3,lc2,lc1;
reg [LC_WIDTH-1:0] lc3_d1,lc2_d1,lc1_d1;
reg [LC_WIDTH-1:0] lc3_d2,lc2_d2,lc1_d2;
reg [LC_WIDTH-1:0] lc3_d3,lc2_d3,lc1_d3; ///fyz修改
//delay la 3 cycles
wire [PRIOR_INFO_WIDTH-1:0] la3,la2,la1;
reg [PRIOR_INFO_WIDTH-1:0] la3_d1,la2_d1,la1_d1;
reg [PRIOR_INFO_WIDTH-1:0] la3_d2,la2_d2,la1_d2;
reg [PRIOR_INFO_WIDTH-1:0] la3_d3,la2_d3,la1_d3;
reg [PRIOR_INFO_WIDTH-1:0] la3_d4,la2_d4,la1_d4; ///fyz修改
reg [1:0] d_hd;
//*************************************************************************
//input rename
//*************************************************************************
assign ys0 = ys[SOFT_INFO_WIDTH-1:0];
assign ys1 = ys[SOFT_INFO_WIDTH*2-1:SOFT_INFO_WIDTH];
//alpha rename
assign alpha7 = alpha[STATE_MATRIC_WIDTH*8-1:STATE_MATRIC_WIDTH*7];
assign alpha6 = alpha[STATE_MATRIC_WIDTH*7-1:STATE_MATRIC_WIDTH*6];
assign alpha5 = alpha[STATE_MATRIC_WIDTH*6-1:STATE_MATRIC_WIDTH*5];
assign alpha4 = alpha[STATE_MATRIC_WIDTH*5-1:STATE_MATRIC_WIDTH*4];
assign alpha3 = alpha[STATE_MATRIC_WIDTH*4-1:STATE_MATRIC_WIDTH*3];
assign alpha2 = alpha[STATE_MATRIC_WIDTH*3-1:STATE_MATRIC_WIDTH*2];
assign alpha1 = alpha[STATE_MATRIC_WIDTH*2-1:STATE_MATRIC_WIDTH*1];
assign alpha0 = alpha[STATE_MATRIC_WIDTH*1-1:STATE_MATRIC_WIDTH*0];
//beta rename
assign beta7 = beta[STATE_MATRIC_WIDTH*8-1:STATE_MATRIC_WIDTH*7];
assign beta6 = beta[STATE_MATRIC_WIDTH*7-1:STATE_MATRIC_WIDTH*6];
assign beta5 = beta[STATE_MATRIC_WIDTH*6-1:STATE_MATRIC_WIDTH*5];
assign beta4 = beta[STATE_MATRIC_WIDTH*5-1:STATE_MATRIC_WIDTH*4];
assign beta3 = beta[STATE_MATRIC_WIDTH*4-1:STATE_MATRIC_WIDTH*3];
assign beta2 = beta[STATE_MATRIC_WIDTH*3-1:STATE_MATRIC_WIDTH*2];
assign beta1 = beta[STATE_MATRIC_WIDTH*2-1:STATE_MATRIC_WIDTH*1];
assign beta0 = beta[STATE_MATRIC_WIDTH*1-1:STATE_MATRIC_WIDTH*0];
//gamma rename
assign gamma15 = gamma[BRANCH_MATRIC_WIDTH*16-1:BRANCH_MATRIC_WIDTH*15];
assign gamma14 = gamma[BRANCH_MATRIC_WIDTH*15-1:BRANCH_MATRIC_WIDTH*14];
assign gamma13 = gamma[BRANCH_MATRIC_WIDTH*14-1:BRANCH_MATRIC_WIDTH*13];
assign gamma12 = gamma[BRANCH_MATRIC_WIDTH*13-1:BRANCH_MATRIC_WIDTH*12];
assign gamma11 = gamma[BRANCH_MATRIC_WIDTH*12-1:BRANCH_MATRIC_WIDTH*11];
assign gamma10 = gamma[BRANCH_MATRIC_WIDTH*11-1:BRANCH_MATRIC_WIDTH*10];
assign gamma9 = gamma[BRANCH_MATRIC_WIDTH*10-1:BRANCH_MATRIC_WIDTH*9];
assign gamma8 = gamma[BRANCH_MATRIC_WIDTH*9-1:BRANCH_MATRIC_WIDTH*8];
assign gamma7 = gamma[BRANCH_MATRIC_WIDTH*8-1:BRANCH_MATRIC_WIDTH*7];
assign gamma6 = gamma[BRANCH_MATRIC_WIDTH*7-1:BRANCH_MATRIC_WIDTH*6];
assign gamma5 = gamma[BRANCH_MATRIC_WIDTH*6-1:BRANCH_MATRIC_WIDTH*5];
assign gamma4 = gamma[BRANCH_MATRIC_WIDTH*5-1:BRANCH_MATRIC_WIDTH*4];
assign gamma3 = gamma[BRANCH_MATRIC_WIDTH*4-1:BRANCH_MATRIC_WIDTH*3];
assign gamma2 = gamma[BRANCH_MATRIC_WIDTH*3-1:BRANCH_MATRIC_WIDTH*2];
assign gamma1 = gamma[BRANCH_MATRIC_WIDTH*2-1:BRANCH_MATRIC_WIDTH*1];
assign gamma0 = gamma[BRANCH_MATRIC_WIDTH*1-1:BRANCH_MATRIC_WIDTH*0];
//*************************************************************************
//cal l
//*************************************************************************
always @(posedge clk_sys) begin
lt37_tmp <= {{3{gamma12[BRANCH_MATRIC_WIDTH-1]}},gamma12} + beta7;
lt36_tmp <= {{3{gamma14[BRANCH_MATRIC_WIDTH-1]}},gamma14} + beta6;
lt35_tmp <= {{3{gamma15[BRANCH_MATRIC_WIDTH-1]}},gamma15} + beta5;
lt34_tmp <= {{3{gamma13[BRANCH_MATRIC_WIDTH-1]}},gamma13} + beta4;
lt33_tmp <= {{3{gamma12[BRANCH_MATRIC_WIDTH-1]}},gamma12} + beta3;
lt32_tmp <= {{3{gamma14[BRANCH_MATRIC_WIDTH-1]}},gamma14} + beta2;
lt31_tmp <= {{3{gamma15[BRANCH_MATRIC_WIDTH-1]}},gamma15} + beta1;
lt30_tmp <= {{3{gamma13[BRANCH_MATRIC_WIDTH-1]}},gamma13} + beta0;
lt27_tmp <= {{3{gamma10[BRANCH_MATRIC_WIDTH-1]}},gamma10} + beta7;
lt26_tmp <= {{3{gamma8[BRANCH_MATRIC_WIDTH-1]}},gamma8} + beta6;
lt25_tmp <= {{3{gamma9[BRANCH_MATRIC_WIDTH-1]}},gamma9} + beta5;
lt24_tmp <= {{3{gamma11[BRANCH_MATRIC_WIDTH-1]}},gamma11} + beta4;
lt23_tmp <= {{3{gamma10[BRANCH_MATRIC_WIDTH-1]}},gamma10} + beta3;
lt22_tmp <= {{3{gamma8[BRANCH_MATRIC_WIDTH-1]}},gamma8} + beta2;
lt21_tmp <= {{3{gamma9[BRANCH_MATRIC_WIDTH-1]}},gamma9} + beta1;
lt20_tmp <= {{3{gamma11[BRANCH_MATRIC_WIDTH-1]}},gamma11} + beta0;
lt17_tmp <= {{3{gamma7[BRANCH_MATRIC_WIDTH-1]}},gamma7} + beta7;
lt16_tmp <= {{3{gamma5[BRANCH_MATRIC_WIDTH-1]}},gamma5} + beta6;
lt15_tmp <= {{3{gamma4[BRANCH_MATRIC_WIDTH-1]}},gamma4} + beta5;
lt14_tmp <= {{3{gamma6[BRANCH_MATRIC_WIDTH-1]}},gamma6} + beta4;
lt13_tmp <= {{3{gamma7[BRANCH_MATRIC_WIDTH-1]}},gamma7} + beta3;
lt12_tmp <= {{3{gamma5[BRANCH_MATRIC_WIDTH-1]}},gamma5} + beta2;
lt11_tmp <= {{3{gamma4[BRANCH_MATRIC_WIDTH-1]}},gamma4} + beta1;
lt10_tmp <= {{3{gamma6[BRANCH_MATRIC_WIDTH-1]}},gamma6} + beta0;
lt07_tmp <= {{3{gamma1[BRANCH_MATRIC_WIDTH-1]}},gamma1} + beta7;
lt06_tmp <= {{3{gamma3[BRANCH_MATRIC_WIDTH-1]}},gamma3} + beta6;
lt05_tmp <= {{3{gamma2[BRANCH_MATRIC_WIDTH-1]}},gamma2} + beta5;
lt04_tmp <= {{3{gamma0[BRANCH_MATRIC_WIDTH-1]}},gamma0} + beta4;
lt03_tmp <= {{3{gamma1[BRANCH_MATRIC_WIDTH-1]}},gamma1} + beta3;
lt02_tmp <= {{3{gamma3[BRANCH_MATRIC_WIDTH-1]}},gamma3} + beta2;
lt01_tmp <= {{3{gamma2[BRANCH_MATRIC_WIDTH-1]}},gamma2} + beta1;
lt00_tmp <= {{3{gamma0[BRANCH_MATRIC_WIDTH-1]}},gamma0} + beta0;
alpha0_d <= alpha0;
alpha1_d <= alpha1;
alpha2_d <= alpha2;
alpha3_d <= alpha3;
alpha4_d <= alpha4;
alpha5_d <= alpha5;
alpha6_d <= alpha6;
alpha7_d <= alpha7;
end
always @ ( posedge clk_sys or negedge rst_b ) begin
if( !rst_b ) begin
lt37 <=1'b0;
lt36 <=1'b0;
lt35 <=1'b0;
lt34 <=1'b0;
lt33 <=1'b0;
lt32 <=1'b0;
lt31 <=1'b0;
lt30 <=1'b0;
lt27 <=1'b0;
lt26 <=1'b0;
lt25 <=1'b0;
lt24 <=1'b0;
lt23 <=1'b0;
lt22 <=1'b0;
lt21 <=1'b0;
lt20 <=1'b0;
lt17 <=1'b0;
lt16 <=1'b0;
lt15 <=1'b0;
lt14 <=1'b0;
lt13 <=1'b0;
lt12 <=1'b0;
lt11 <=1'b0;
lt10 <=1'b0;
lt07 <=1'b0;
lt06 <=1'b0;
lt05 <=1'b0;
lt04 <=1'b0;
lt03 <=1'b0;
lt02 <=1'b0;
lt01 <=1'b0;
lt00 <=1'b0;
end
else begin
if( l_source_val_d1 ) begin
lt37 <= alpha1_d + lt37_tmp;
lt36 <= alpha3_d + lt36_tmp;
lt35 <= alpha4_d + lt35_tmp;
lt34 <= alpha6_d + lt34_tmp;
lt33 <= alpha0_d + lt33_tmp;
lt32 <= alpha2_d + lt32_tmp;
lt31 <= alpha5_d + lt31_tmp;
lt30 <= alpha7_d + lt30_tmp;
lt27 <= alpha7_d + lt27_tmp;
lt26 <= alpha5_d + lt26_tmp;
lt25 <= alpha2_d + lt25_tmp;
lt24 <= alpha0_d + lt24_tmp;
lt23 <= alpha6_d + lt23_tmp;
lt22 <= alpha4_d + lt22_tmp;
lt21 <= alpha3_d + lt21_tmp;
lt20 <= alpha1_d + lt20_tmp;
lt17 <= alpha0_d + lt17_tmp;
lt16 <= alpha2_d + lt16_tmp;
lt15 <= alpha5_d + lt15_tmp;
lt14 <= alpha7_d + lt14_tmp;
lt13 <= alpha1_d + lt13_tmp;
lt12 <= alpha3_d + lt12_tmp;
lt11 <= alpha4_d + lt11_tmp;
lt10 <= alpha6_d + lt10_tmp;
lt07 <= alpha6_d + lt07_tmp;
lt06 <= alpha4_d + lt06_tmp;
lt05 <= alpha3_d + lt05_tmp;
lt04 <= alpha1_d + lt04_tmp;
lt03 <= alpha7_d + lt03_tmp;
lt02 <= alpha5_d + lt02_tmp;
lt01 <= alpha2_d + lt01_tmp;
lt00 <= alpha0_d + lt00_tmp;
end
else begin
lt37 <= lt37;
lt36 <= lt36;
lt35 <= lt35;
lt34 <= lt34;
lt33 <= lt33;
lt32 <= lt32;
lt31 <= lt31;
lt30 <= lt30;
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