mod_max4.v

上传的是WIMAX系统中

//FILE_HEADER------------------------------------------------------------------
//Copyright: 2006 ZTE CORPORATION
//Company Confidential: This proprietary may be used only as authorized by a 
//                      agreement from WiMAX Department of ZTE CORPORATION.  
//----------------------------------------------------------------------------
//FILENAME       : mod_max4.v
//DEPARTMENT     : WiMAX department
//AUTHOR         : yuanliuqing
//AUTHOR'S EMAIL : [e-mail]
//----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION      DATE         AUTHOR       DESCRIPTION
// 0.1       2006-7-21     yuanliuqing   create
//---------------------------------------------------------------------------- 
//KEYWORDS       : CTC MAX-LOG-MAP decoder
//----------------------------------------------------------------------------
//PURPOSE        : mod_max operation(modulo normaliztion) for alpha/beta calculation
//----------------------------------------------------------------------------
//PARAMETERS    
//PARAM NAME:        RANGE:            DESCRIPTION:        DEFAULT:   UNITS:
//
//----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy     : 
//Clock  Domains     : pure comb logic
//Critical Timing    : N/A
//Test   Features    : N/A
//Asynchronous I/F   : rst_b
//Scan Methodology   : Mux-D
//Instaniations      : N/A
//Synthesizable      : Yes
//Other              : N/A
//END_HEADER------------------------------------------------------------------

`timescale 1ns/100ps

module mod_max4
    (
        //input
        a,
        b,
        c,
        d,
        //output
        e
    );
    //*************************************************************************
    //parameters
    parameter       STATE_MATRIC_WIDTH = 6'd12;
    //*************************************************************************
    //ports direction
    //input
    input  [STATE_MATRIC_WIDTH-1:0]  a;
    input  [STATE_MATRIC_WIDTH-1:0]  b;
    input  [STATE_MATRIC_WIDTH-1:0]  c;
    input  [STATE_MATRIC_WIDTH-1:0]  d;
    //output
    output  [STATE_MATRIC_WIDTH-1:0]  e;
    //*************************************************************************
    //ports type
    //input
    wire    [STATE_MATRIC_WIDTH-1:0]  a;
    wire    [STATE_MATRIC_WIDTH-1:0]  b;
    wire    [STATE_MATRIC_WIDTH-1:0]  c;
    wire    [STATE_MATRIC_WIDTH-1:0]  d;
    //output
    reg    [STATE_MATRIC_WIDTH-1:0]  e;
    //*************************************************************************

    wire    [STATE_MATRIC_WIDTH-1:0]   r0,r1,r2,r3,r4,r5;
    
    //************************************************************
    // all variables are signed
    //************************************************************
    
//    assign  r0[STATE_MATRIC_WIDTH-1:0] = a[STATE_MATRIC_WIDTH-1:0] - b[STATE_MATRIC_WIDTH-1:0];   //natural overflow
//    assign  r1[STATE_MATRIC_WIDTH-1:0] = c[STATE_MATRIC_WIDTH-1:0] - d[STATE_MATRIC_WIDTH-1:0];   //natural overflow
//    assign  r2[STATE_MATRIC_WIDTH-1:0] = aa[STATE_MATRIC_WIDTH-1:0] - bb[STATE_MATRIC_WIDTH-1:0]; //natural overflow
/*
    sub12 sub12_u1
    (
    	.dataa   (a),
    	.datab   (b),
    	.result  (r0)
	);

    sub12 sub12_u2
    (
    	.dataa   (c),
    	.datab   (d),
    	.result  (r1)
	);
	
    sub12 sub12_u3
    (
    	.dataa   (aa),
    	.datab   (bb),
    	.result  (r2)
	);
		    
    assign  aa = (!r0[STATE_MATRIC_WIDTH-1]) ? a:b;
    assign  bb = (!r1[STATE_MATRIC_WIDTH-1]) ? c:d;
    assign  e = (!r2[STATE_MATRIC_WIDTH-1]) ? aa:bb;
  */
  
  assign r0 = a - b;
  assign r1 = a - c;
  assign r2 = a - d;
  assign r3 = b - c;
  assign r4 = b - d;
  assign r5 = c - d;
  
  wire[5:0] aa = {r0[STATE_MATRIC_WIDTH-1], r1[STATE_MATRIC_WIDTH-1],
                  r2[STATE_MATRIC_WIDTH-1], r3[STATE_MATRIC_WIDTH-1],
                  r4[STATE_MATRIC_WIDTH-1], r5[STATE_MATRIC_WIDTH-1]};
  
  
  always @(*)
  /*  casex (aa)
	    6'b000xxx : e = a;
	    6'b1xx00x : e = b;
	    6'bx1x1x0 : e = c;
	    default : e = d;
    endcase  */
      case (aa)
          6'b000000,6'b000001,6'b000010,6'b000011,6'b000100,6'b000101,6'b000110,6'b000111 : e = a;
          6'b100000,6'b100001,6'b101000,6'b101001,6'b110000,6'b110001,6'b111000,6'b111001 : e = b;
          6'b010100,6'b010110,6'b011100,6'b011110,6'b110100,6'b110110,6'b111100,6'b111110 : e = c;
          default : e = d;
      endcase

/*
  always @(*)
    if({r0[STATE_MATRIC_WIDTH-1], r1[STATE_MATRIC_WIDTH-1],r2[STATE_MATRIC_WIDTH-1]} == 3'b000)
      e = a;
    else if({r0[STATE_MATRIC_WIDTH-1], r3[STATE_MATRIC_WIDTH-1],r4[STATE_MATRIC_WIDTH-1]} == 3'b100)
      e = b;
    else if({r1[STATE_MATRIC_WIDTH-1], r3[STATE_MATRIC_WIDTH-1],r5[STATE_MATRIC_WIDTH-1]} == 3'b110)
      e = c;
    else
      e = d;
  */
  
  
    
endmodule