ctc_mctrl.v

上传的是WIMAX系统中

       
reg sop1;
reg sop2;
reg sop3;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
          sop1 <= 1'b0;
          sop2 <= 1'b0;
          sop3 <= 1'b0;
    sop_source <= 1'b0;
    end
    else if(st_current==RD && (~|fwin_cnt)) begin
          sop1 <= 1'b1;
          sop2 <= sop1;
          sop3 <= sop2;
    sop_source <= sop3;
    end
    else begin
          sop1 <= 1'b0;
          sop2 <= sop1;
          sop3 <= sop2;
    sop_source <= sop3;
    end
end
///**************************************************************************
///eop_source信号生成
///**************************************************************************
reg eop1;
reg eop2;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
          eop1 <= 1'b0;
          eop2 <= 1'b0;
    eop_source <= 1'b0;
    end
    else if(st_current==RD && (win_cnt==6'd32)) begin
          eop1 <= 1'b1;
          eop2 <= eop1;
    eop_source <= eop2;
    end
    else begin
          eop1 <= 1'b0;
          eop2 <= eop1;
    eop_source <= eop2;
    end
end
///**************************************************************************
///val_source信号生成                                                       
///**************************************************************************       
reg val1;
reg val2;
reg val3;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
          val1 <= 1'b0;
          val2 <= 1'b0;
          val3 <= 1'b0;
    val_source <= 1'b0;
    end
    else if(st_current==RD && (win_cnt<6'd32)) begin
          val1 <= 1'b1;
          val2 <= val1;
          val3 <= val2;
    val_source <= val3;
    end
    else begin
          val1 <= 1'b0;
          val2 <= val1;
          val3 <= val2;
    val_source <= val3;
    end
end

///**************************************************************************
///le_ram用来缓存外部信息，因为是利用活动窗分段译码算法，
///而且要同时完成解交织，所以需要两块RAM来完成。
///顺序写入，利用交织地址读出，可以完成交织过程；
///顺序写入，利用解交织地址读出，就是解交织过程
///le_ram中存放外部信息用于分支度量计算
///**************************************************************************

//interface with le_ram
reg           le_wr0;
reg           le_wr1;
reg   [11:0]  le_wradr0;
reg   [11:0]  le_wradr1;
reg   [23:0]  le_din0;
reg   [23:0]  le_din1;

reg           le_rd0;
reg           le_rd1;
reg   [11:0]  le_rdadr0;
reg   [11:0]  le_rdadr1;

reg   [5:0]   w0_cnt;
       
//外部信息写计数器:w0_cnt
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        w0_cnt <= 6'b0;
    else if(w0_cnt==6'd31)
        w0_cnt <= 6'b0;
    else if(dec_no[0] & val_sink)
        w0_cnt <= w0_cnt + 1'b1;
end

//输入的le的值在每个滑动窗都是逆序的，需要在写入
//存储器时将次序调整过来
reg   [11:0]  ADDR0;
//FEC块个数计数器
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        ADDR0 <= 12'b0;
    else if(w0_cnt==6'd31)
        ADDR0 <= 12'd32;
    else if(st_current==DEC_AD)
        ADDR0 <= 12'b0;
end

//RAM0写
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        le_wr0    <= 1'b0;
        le_wradr0 <= 12'b0;
        le_din0   <= 24'b0;
    end
    else if(dec_no[0] & val_sink) begin
        le_wr0  <= 1'b1;
        le_din0 <= le;
        if(~|w0_cnt)
            le_wradr0 <= le_wradr0 + 12'd31 + ADDR0;
        else
            le_wradr0 <= le_wradr0 - 1'b1;
    end
    else if(eop_sink | dec_end) begin
        le_wr0    <= 1'b0;
        le_wradr0 <= 12'b0;
        le_din0   <= 24'b0;
    end
    else begin
        le_wr0    <= 1'b0;
        le_wradr0 <= le_wradr0;
        le_din0   <= le_din0;
    end
end

//RAM0读
reg          rd0;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
           rd0     <= 1'b0;
        le_rd0     <= 1'b0;
        le_rdadr0  <= 12'd0;
    end
    //同滑动窗对应起来
    else if(~|dec_no) begin
           rd0 <= 1'b0;
        le_rd0 <= rd0;
     le_rdadr0 <= 12'd0;              //mahui for test 070710
    end
    else if((~dec_no[0]) & (st_current==RD)) begin
           rd0    <= 1'b1;
        le_rd0    <= rd0;
        le_rdadr0 <= llrde_addr;
    end
    else begin
           rd0    <= 1'b0;
        le_rd0    <= rd0;
        le_rdadr0 <= 12'd0;         //mahui for test 070710
    end
end

reg   [5:0]   w1_cnt;
//外部信息写计数器:w1_cnt
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        w1_cnt <= 6'b0;
    else if(w1_cnt==6'd31)
        w1_cnt <= 6'b0;
    else if(~dec_no[0] & val_sink)
        w1_cnt <= w1_cnt + 1'b1;
end

reg   [11:0]  ADDR1;
//FEC块个数计数器
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        ADDR1 <= 12'b0;
    else if(w1_cnt==6'd31)
        ADDR1 <= 12'd32;
    else if(st_current==DEC_AD)
        ADDR1 <= 12'b0;
end

//RAM1写
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        le_wr1    <= 1'b0;
        le_wradr1 <= 12'b0;
        le_din1   <= 24'b0;
    end
    else if((~dec_no[0]) & val_sink) begin
        le_wr1  <= 1'b1;
        le_din1 <= le;
        if(~|w1_cnt)
            le_wradr1 <= le_wradr1 + 12'd31 + ADDR1;
        else
            le_wradr1 <= le_wradr1 - 1'b1;
    end
    else if(eop_sink | dec_end) begin
        le_wr1    <= 1'b0;
        le_wradr1 <= 12'b0;
        le_din1   <= 24'b0;
    end
    else begin
        le_wr1    <= 1'b0;
        le_wradr1 <= le_wradr1;
        le_din1   <= le_din1;
    end
end

//RAM1读
reg rd1;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
           rd1    <= 1'b0;
        le_rd1    <= 1'b0;
        le_rdadr1 <= 12'd0;
    end
    //同滑动窗对应起来
    else if(dec_no[0]&&(st_current == RD)) begin
           rd1    <= 1'b1;
        le_rd1    <= rd1;
        le_rdadr1 <= dat_addr;
    end
    else begin
          rd1     <= 1'b0;
        le_rd1    <= rd1;
        le_rdadr1 <= 12'd0;                      //mahui for test 070710
    end
end

le_ram  le_ram_u1 (
        .clock     ( sys_clk       ),
        .data      ( le_din0[23:0] ),
        .rdaddress ( le_rdadr0     ),
        .rden      ( le_rd0        ),
        .wraddress ( le_wradr0     ),
        .wren      ( le_wr0        ),
        .q         ( le_dout0[23:0])
        );

le_ram  le_ram_u2 (
        .clock     ( sys_clk       ),
        .data      ( le_din1[23:0] ),
        .rdaddress ( le_rdadr1     ),
        .rden      ( le_rd1        ),
        .wraddress ( le_wradr1     ),
        .wren      ( le_wr1        ),
        .q         ( le_dout1[23:0])
        );

//译码结束信号
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        dec_finish <= 1'b0;
    else if(dec_end | ((dec_no>=ctrl2resm_miter) & (st_current==DEC_AD)))
        dec_finish <= 1'b1;
    else if(core_gnt)
        dec_finish <= 1'b0;
end

///包头信息
       always @(negedge reset_b or posedge sys_clk) begin
           if(!reset_b) begin
                       length_1         <= 16'd0;
               ctrl2resm_length         <= 16'd0;
               ctrl2resm_type           <= 3'd0;
               ctrl2resm_frame_end_flag <=3'd0;   //add by mahui 070704
               ctrl2resm_inst           <= 2'd0;             
               ctrl2resm_code_rate      <= 3'd0;
               ctrl2resm_modu_type      <= 2'd0;
               ctrl2resm_bnum           <= 16'd0;
               ctrl2resm_fnum           <= 8'd0;
               ctrl2resm_miter          <= 4'd0;
               ctrl2resm_segId          <= 4'd0;   //Segment ID  add by mahui 070704       
           end 
           //else if(st_current == WAIT && wr_over)
           else if(st_current == WAIT) begin
                       length_1         <= rx2ctrl_length - 16'b1;            
               ctrl2resm_length         <= rx2ctrl_length;  
               ctrl2resm_type           <= rx2ctrl_type; 
               ctrl2resm_frame_end_flag <= rx2ctrl_frame_end_flag;  //add by mahui 070704
               ctrl2resm_inst           <= rx2ctrl_inst;                 
               ctrl2resm_code_rate      <= rx2ctrl_code_rate;
               ctrl2resm_modu_type      <= rx2ctrl_modu_type;
               ctrl2resm_bnum           <= rx2ctrl_bnum;    
               ctrl2resm_fnum           <= rx2ctrl_fnum;    
               ctrl2resm_miter          <= rx2ctrl_miter;              
               ctrl2resm_segId          <= rx2ctrl_segId;   //Segment ID  add by mahui 070704       
           end 
       end                 
endmodule  ///ctc_mctrl