ctc_mctrl.v

上传的是WIMAX系统中

    else if(st_next==DEC_AD)
        dec_no <= dec_no + 1'b1;
end

///**************************************************************************
///dpram读使能信号产生
///**************************************************************************
reg   ram1_rd;
reg   ram2_rd;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        ram1_rd   <= 1'b0;
        ram2_rd   <= 1'b0;
        dpram1_rd <= 1'b0;
        dpram2_rd <= 1'b0;
    end
    else if(st_current==RD) begin
        ram1_rd   <= 1'b1;
        ram2_rd   <= 1'b1;
        dpram1_rd <= ram1_rd;
        dpram2_rd <= ram2_rd;
    end
    else begin
        ram1_rd   <= 1'b0;
        ram2_rd   <= 1'b0;
        dpram1_rd <= ram1_rd;
        dpram2_rd <= ram2_rd;
    end
end
///**************************************************************************
///dpram读地址产生
///**************************************************************************
reg  [11:0]   ram1_rdadr;
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b) begin
        ram1_rdadr   <= 12'b0;
        dpram1_rdadr <= 12'b0;
    end
    else begin
        case(st_current)
            DEC_AD: begin
                 ram1_rdadr   <= 12'b0;
                 dpram1_rdadr <= 12'b0;
            end
            RD: begin
                if(dec_no[0])
                    dpram1_rdadr <= dat_addr;
                else begin
                    dpram1_rdadr <= ram1_rdadr;
                    case(ctrl2resm_length[13:0])
                        14'd24:
                            if(fwin_cnt==6'd0)
                                ram1_rdadr <= 12'd16;
                            else if(fwin_cnt==6'd8 | (fwin_cnt==WIN_SIZE & fec_cnt[5:0]==6'd0)
                                    | fec_cnt[5:0]==ctrl2resm_length[5:0] | win_cnt==6'd16)
                                ram1_rdadr <= 12'b0;
                            else
                                ram1_rdadr <= ram1_rdadr + 1'b1;
                        14'd36:
                            if(fwin_cnt==6'd0)
                                ram1_rdadr <= 12'd4;
                            else if((fwin_cnt==WIN_SIZE & fec_cnt[6:0]==7'd0) | fec_cnt[6:0]==ctrl2resm_length[6:0] | win_cnt == 6'd8)
                                ram1_rdadr <= 12'b0;
                            else
                                ram1_rdadr <= ram1_rdadr + 1'b1;
                        default:
                            if(fwin_cnt==6'd0)
                                ram1_rdadr <= ctrl2resm_length[11:0] - 12'd32;
                            else if((fwin_cnt==WIN_SIZE & fec_cnt==14'd0) | fec_cnt==ctrl2resm_length[13:0])
                                ram1_rdadr <= 12'b0;
                            else
                                ram1_rdadr <= ram1_rdadr + 1'b1;
                    endcase
                end
            end
            default: begin
                ram1_rdadr   <= ram1_rdadr;
                dpram1_rdadr <= dpram1_rdadr;
            end
        endcase
    end
end
///**************************************************************************
///dpram读地址产生
///**************************************************************************
reg  [11:0]   ram2_rdadr;
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b) begin
        ram2_rdadr   <= 12'b0;
        dpram2_rdadr <= 12'b0;
    end
    else begin
        case(st_current)
            DEC_AD: begin
                ram2_rdadr   <= 12'b0;
                dpram2_rdadr <= 12'b0;
            end
            RD: begin
                dpram2_rdadr <= ram2_rdadr;
                case(ctrl2resm_length[13:0])
                    14'd24:
                        if(fwin_cnt==6'd0)
                            ram2_rdadr <= 12'd16;
                        else if(fwin_cnt==6'd8 | (fwin_cnt==WIN_SIZE & fec_cnt[5:0]==6'd0)
                                | fec_cnt[5:0]==ctrl2resm_length[5:0] | win_cnt == 6'd16)
                            ram2_rdadr <= 12'b0;
                        else
                            ram2_rdadr <= ram2_rdadr + 1'b1;
                    14'd36:
                        if (fwin_cnt == 6'd0)
                            ram2_rdadr <= 12'd4;
                        else if ((fwin_cnt==WIN_SIZE&fec_cnt[6:0]==7'd0) | fec_cnt[6:0]==ctrl2resm_length[6:0] | win_cnt == 6'd8)
                            ram2_rdadr <= 12'b0;
                        else
                            ram2_rdadr <= ram2_rdadr + 1'b1;
                    default:
                        if (fwin_cnt == 6'd0)
                            ram2_rdadr <= ctrl2resm_length[11:0] - 12'd32;
                        else if((fwin_cnt==WIN_SIZE & fec_cnt==14'd0) | fec_cnt == ctrl2resm_length[13:0])
                            ram2_rdadr <= 12'b0;
                        else
                            ram2_rdadr <= ram2_rdadr + 1'b1;
                    endcase
            end
            default: begin
                ram2_rdadr   <= ram2_rdadr;
                dpram2_rdadr <= dpram2_rdadr;
            end
        endcase
    end
end
///**************************************************************************
///交织模块使能信号，为1时，交织/解交织地址开始生成
///**************************************************************************
always @(negedge reset_b or posedge sys_clk) begin 
    if(!reset_b)
        mctrl2dat_en <= 1'b0;
    else if(st_current==WAIT && wr_over)
        mctrl2dat_en <= 1'b1;
    else
        mctrl2dat_en <= 1'b0;
end
///**************************************************************************
///交织地址读接口信号     
///**************************************************************************
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        mctrl2dat_rd   <= 1'b0;
        mctrl2dat_addr <= 12'b0;
    end
    else if(st_current==DEC_AD & dec_no[0] & (dec_no<ctrl2resm_miter)) begin
        mctrl2dat_rd <= 1'b1;
        if (ctrl2resm_length[13:0]<WIN_SIZE)
            mctrl2dat_addr <= 12'd16;
        else
            mctrl2dat_addr <= ctrl2resm_length[11:0] - 12'd32;
    end
    else if (st_current==RD & dec_no[0] & (dec_no<ctrl2resm_miter)) begin
        mctrl2dat_rd <= 1'b1;
        case(ctrl2resm_length[13:0])
            14'd24:
                if(fwin_cnt==6'd7 | fwin_cnt==WIN_SIZE-1 | fec_cnt[5:0]==length_1[5:0] | win_cnt==6'd15)
                    mctrl2dat_addr <= 12'b0;
                else
                    mctrl2dat_addr <= mctrl2dat_addr + 1'b1;
            14'd36:
                if(fwin_cnt==WIN_SIZE-1 | fec_cnt[6:0]==length_1[6:0] | win_cnt==6'd7)
                    mctrl2dat_addr <= 12'b0;
                else
                    mctrl2dat_addr <= mctrl2dat_addr + 1'b1;
            default:
                if(fwin_cnt==WIN_SIZE-1 | fec_cnt[13:0]==length_1[13:0])
                    mctrl2dat_addr <= 12'b0;
                else
                    mctrl2dat_addr <= mctrl2dat_addr + 1'b1;
        endcase
    end
    else begin
        mctrl2dat_rd   <=1'b0;
        mctrl2dat_addr <=12'b0;
    end
end
///**************************************************************************
///解交织地址读接口信号     
///解交织模块使能信号
///**************************************************************************

always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        mctrl2llrde_rd   <= 1'b0;
        mctrl2llrde_addr <= 12'b0;
    end
    else if(dec_no==4'b0) begin
        mctrl2llrde_rd   <= 1'b0;
        mctrl2llrde_addr <= 12'b0;
    end
    else if(st_current==DEC_AD & ~dec_no[0] & (dec_no<ctrl2resm_miter)) begin
        mctrl2llrde_rd <= 1'b1;
        if(ctrl2resm_length[13:0]<WIN_SIZE)
            mctrl2llrde_addr <= 12'd16;
        else
            mctrl2llrde_addr <= ctrl2resm_length[11:0] - 12'd32;
    end
    else if (st_current==RD & ~dec_no[0] & (dec_no<ctrl2resm_miter)) begin
        mctrl2llrde_rd <= 1'b1;
        case (ctrl2resm_length[13:0])
            14'd24:
                if(fwin_cnt==6'd7 | fwin_cnt==WIN_SIZE-1 | fec_cnt[5:0]==length_1[5:0] | win_cnt==6'd15)
                    mctrl2llrde_addr <= 12'b0;
                else
                    mctrl2llrde_addr <= mctrl2llrde_addr + 1'b1;
            14'd36:
                if(fwin_cnt==WIN_SIZE-1 | fec_cnt[6:0]==length_1[6:0] | win_cnt==6'd7)
                    mctrl2llrde_addr <= 12'b0;
                else
                    mctrl2llrde_addr <= mctrl2llrde_addr + 1'b1;
            default:
                if(fwin_cnt==WIN_SIZE-1 | fec_cnt[13:0]==length_1[13:0])
                    mctrl2llrde_addr <= 12'b0;
                else
                    mctrl2llrde_addr <= mctrl2llrde_addr + 1'b1;
        endcase
    end
    else begin
        mctrl2llrde_rd   <=1'b0;
        mctrl2llrde_addr <=12'b0;
    end
end
///**************************************************************************
///数据交替置换     
///
///**************************************************************************
reg  [11:0]  llrde_addr1;
reg  [11:0]  llrde_addr2;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        llrde_addr1 <= 12'h0;
        llrde_addr2 <= 12'h0;
    end
    else begin
        llrde_addr1 <= mctrl2llrde_addr;
        llrde_addr2 <= llrde_addr1;
    end
end

reg  [11:0]   dat1_adr;

///**************************************************************************
///滑动窗口的处理: 由dpram读地址产生
///dpram读地址产生
///**************************************************************************
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) 
        dat1_adr <= 12'b0;
    else 
        dat1_adr <= dpram1_rdadr;
end

///**************************************************************************
//interface with ctc_map module
//根据CTC算法进行确定,注意考虑双二进制
//数据输入
///**************************************************************************
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b) begin
        ys <= 12'b0;
        yp <= 12'b0;
    end
    else if(st_current==RD | st_current==EOP) begin
        if(dat1_adr[0] & dec_no[0])
            ys <= {dpram1_rddat[5:0],dpram1_rddat[11:6]};
        else
            ys <= dpram1_rddat[11:0];
        if(~dec_no[0])
            yp <= {dpram2_rddat[17:12],dpram2_rddat[5:0]};
        else
            yp <= {dpram2_rddat[23:18],dpram2_rddat[11:6]};
    end
    else begin
        ys <= ys;
        yp <= yp;
    end
end

///**************************************************************************
///先验信息输出 
///**************************************************************************
wire  [23:0]  le_dout0;
wire  [23:0]  le_dout1;
always @(negedge reset_b or posedge sys_clk) begin
    if(!reset_b)
        la <= 24'b0;
    else if(dec_no==4'b0)
        la <= 24'b0;
    else if((st_current==RD | st_current==EOP) & ~dec_no[0])
        la <= (llrde_addr2[0]) ? le_dout0 : {le_dout0[23:16],le_dout0[7:0],le_dout0[15:8]};
    else if((st_current==RD | st_current==EOP) & dec_no[0])
        la <= dat1_adr[0] ? {le_dout1[23:16],le_dout1[7:0],le_dout1[15:8]} : le_dout1;
    else
        la <= la;
end

///**************************************************************************
///sop_source信号生成
///**************************************************************************