stop_detect.v

上传的是WIMAX系统中

        if( !rst_b )
            rd_ram_adr_counter <= WIN_SIZE-1'd1;
        else if( clr_stop_detect )
            rd_ram_adr_counter <= WIN_SIZE-1'd1;
        else if( rd_en )
            if( counter_mod_winsize_rd==8'd0 )
                rd_ram_adr_counter <= rd_ram_adr_counter+WIN_SIZE*2'd2-1'd1;
            else
                rd_ram_adr_counter <= rd_ram_adr_counter-1'd1;
        else
            rd_ram_adr_counter <= WIN_SIZE-1'd1;
    end
    //assign int/deint index ram adr to rd_ram_adr_counter
    assign   eff_adr_flag = (rd_ram_adr_counter<packet_length);
    assign   adr_rd_int_ram =  eff_adr_flag ? rd_ram_adr_counter:(rd_ram_adr_counter-packet_length[11:0]);
    assign   adr_rd_deint_ram = eff_adr_flag ? rd_ram_adr_counter:(rd_ram_adr_counter-packet_length[11:0]);

    always @(posedge clk_sys or negedge rst_b) begin
        if(!rst_b)
            {eff_adr_flag_d3,eff_adr_flag_d2,eff_adr_flag_d1} <= 3'b000;
        else
            {eff_adr_flag_d3,eff_adr_flag_d2,eff_adr_flag_d1}
                 <= {eff_adr_flag_d2,eff_adr_flag_d1,eff_adr_flag};
    end
    //hd_bit_ram_rd_adr selection:
    //  1: interleave
    //  0: deinterleave

    always @ ( posedge clk_sys )
        case( wr_ping_pong_flag )
            1'b1:
                hd_bit_ram_rd_adr <= dat_rd_int_ram;
            1'b0:
                hd_bit_ram_rd_adr <= dat_rd_deint_ram + 13'd4096;
            default:
                hd_bit_ram_rd_adr <= 1'b0;
        endcase


    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            iter_num_counter <= 1'b0;
        else begin
            if( clr_stop_detect )
                iter_num_counter <= 1'b0;
            else if( eop_sink_d3 )  ///fyz
                iter_num_counter <= iter_num_counter + 1'b1;
            else
                iter_num_counter <= iter_num_counter;
        end
    end

    assign real_iter_no = iter_num_counter;


    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {wr_ping_pong_flag_d3,wr_ping_pong_flag_d2,wr_ping_pong_flag_d1} <= 1'b0;
        else
            {wr_ping_pong_flag_d3,wr_ping_pong_flag_d2,wr_ping_pong_flag_d1}
              <= {wr_ping_pong_flag_d2,wr_ping_pong_flag_d1,wr_ping_pong_flag};  ///fyz修改
    end


///注意：sop_sink_d2有效时，可以认为是将compare_result初始化为0。另外，长度为24的最短包只进行一次比较，val_sink也只维持一次比较的长度，不需要特别进行说明

      reg compare_result;
      always @ ( posedge clk_sys or negedge rst_b ) begin
          if( !rst_b )
              compare_result <= 1'b0;
          else if(sop_sink_d2)
              compare_result <= 1'b0;
          else if( val_sink_d3 && eff_adr_flag_d3 )
              if( (!wr_ping_pong_flag_d3 && !dat_rd_deint_ram_d2[0])
                  || (wr_ping_pong_flag_d3 && !adr_rd_int_ram_d3[0]) )
                  compare_result <= compare_result | (d_d3!=={dat_rd_hd_bit_ram[0],dat_rd_hd_bit_ram[1]});
              else
                  compare_result <= compare_result | (d_d3!==dat_rd_hd_bit_ram);
          else
              compare_result <= compare_result;
      end


    //delay d,val_sink,sop_sink, eop_sink
    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {d_d3,d_d2,d_d1} <= 1'b0;    ///fyz修改
        else
            {d_d3,d_d2,d_d1} <= {d_d2,d_d1,d};   ///fyz修改
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {val_sink_d3,val_sink_d2,val_sink_d1} <= 2'b00;   ///fyz修改
        else
            {val_sink_d3,val_sink_d2,val_sink_d1} <= {val_sink_d2,val_sink_d1,val_sink};  ///fyz修改
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {sop_sink_d2,sop_sink_d1} <= 2'b00;
        else
            {sop_sink_d2,sop_sink_d1} <= {sop_sink_d1,sop_sink};
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {eop_sink_d4,eop_sink_d3,eop_sink_d2,eop_sink_d1} <= 3'b000;  ///fyz
        else
            {eop_sink_d4,eop_sink_d3,eop_sink_d2,eop_sink_d1} <= {eop_sink_d3,eop_sink_d2,eop_sink_d1,eop_sink};
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {adr_rd_int_ram_d3,adr_rd_int_ram_d2,adr_rd_int_ram_d1} <= 12'd0;
        else
            {adr_rd_int_ram_d3,adr_rd_int_ram_d2,adr_rd_int_ram_d1} <= {adr_rd_int_ram_d2,adr_rd_int_ram_d1,adr_rd_int_ram};
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {dat_rd_deint_ram_d2,dat_rd_deint_ram_d1} <= 12'd0;  ///fyz修改
        else
            {dat_rd_deint_ram_d2,dat_rd_deint_ram_d1} <= {dat_rd_deint_ram_d1,dat_rd_deint_ram}; ///fyz修改
    end

    //*************************************************************************
    //stop_detect module control fsm
    //*************************************************************************

    always @ ( posedge clk_sys or negedge rst_b ) begin
            if( !rst_b )
                detect_state_current <= READY;
            else
                detect_state_current <= detect_state_next;
        end


    always @ ( * ) begin
        case( detect_state_current )
            READY:
                if( sop_sink )
                    detect_state_next = FILL_IN;
                else
                    detect_state_next = READY;
            FILL_IN:
                if( eop_sink_d4 )  ///fyz
                    detect_state_next = RUN;
                else
                    detect_state_next = FILL_IN;
            RUN:
                if( eop_sink_d4 && ( !compare_result || (iter_num_counter)==max_iter_no ) )
                    detect_state_next = OUTPUT;
                else
                    detect_state_next = RUN;
            OUTPUT:
                detect_state_next = READY;
            default:
                detect_state_next = READY;
        endcase
    end

    //fsm output
    assign  rd_en = (detect_state_current==RUN) && val_sink;
    assign  rd_int_ram = rd_en;
    assign  rd_deint_ram = rd_en;

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            {rd_ram_d1,rd_ram} <= 1'b0;
        else
            {rd_ram_d1,rd_ram} <= {rd_ram,rd_en};
    end
    
    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            iter_stop <= 1'b0;
        else if( detect_state_current==OUTPUT )
            iter_stop <= 1'b1;
        else
            iter_stop <= 1'b0;
    end

    assign  clr_stop_detect = iter_stop;


endmodule  ///stop_detect