stop_detect.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : stop_detect.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : stop_detect
/// Called by    : ctc_decoder_datapath_top  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// stop_detect-----|----hd_bit_ping_pong_ram
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-26  | 建立文件
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核迭代停止判定模块
///*********************************************************************

`timescale 1ns/100ps

module stop_detect
    #(parameter WIN_SIZE            = 6'd32,        ///sliding window size, unit: lattice
                HD_DAT_WIDTH        = 6'd2,         ///dual binary
                PRIOR_INFO_WIDTH    = 6'd8,         ///8-b
                LLR_INFO_WIDTH      = 6'd12     )   ///对数似然比数据宽度
    (
    ///system i/f
    input              clk_sys,                     ///系统时钟信号
    input              rst_b,                       ///输入复位信号
    ///max-log-map i/f
    input       [HD_DAT_WIDTH-1:0]       d,         ///output hard-decision data
    input       [PRIOR_INFO_WIDTH*3-1:0] le,        ///output extrinsic info.backup, not use until now
    input       [LLR_INFO_WIDTH*3-1:0]   l,         ///output bit-pair llr.backup, not use until now
    input              sop_sink,
    input              eop_sink,
    input              val_sink,
    ///packet para i/f
    input       [15:0] packet_length,               ///包长
    input       [2:0]  code_rate,                   ///backup, not use until now
    input       [1:0]  modulate_type,               ///backup, not use until now
    input       [3:0]  max_iter_no,                 ///最大迭代次数
    ///iter_stop i/f
    output wire [4:0]  real_iter_no,                ///实际迭代次数
    output reg         iter_stop,                   ///迭代停止信号
    ///int/deint index i/f
    output wire        rd_int_ram,                  ///交织地址ram读信号
    input       [11:0] dat_rd_int_ram,              ///交织地址ram输出数据线
    output wire [11:0] adr_rd_int_ram,              ///交织地址ram读地址
    output wire        rd_deint_ram,                ///解交织地址ram读信号
    input       [11:0] dat_rd_deint_ram,            ///解交织地址ram输出数据线
    output wire [11:0] adr_rd_deint_ram             ///解交织地址ram读地址
    );

///*********************************************************************
///local parameter define：(本地参数：)
///*********************************************************************
///state define for stop detecting fsm
parameter   READY       = 4'b0001,                  ///等待就绪
            FILL_IN     = 4'b0010,                  ///数据输入
            RUN         = 4'b0100,                  ///硬判决数据比较
            OUTPUT      = 4'b1000;                  ///数据输出

///*********************************************************************
///内部信号定义
///*********************************************************************
    reg     [12:0]                     hd_bit_ram_wr_adr;
    reg     [12:0]                     hd_bit_ram_rd_adr;
    reg                                wr_ping_pong_flag;
    reg     [11:0]                     wr_ram_adr_counter;
    reg     [11:0]                     rd_ram_adr_counter;
    reg     [4:0]                      iter_num_counter;
    reg     [1:0]                      d_d1,d_d2,d_d3;
    reg                                val_sink_d1,val_sink_d2,val_sink_d3;
    reg                                sop_sink_d1,sop_sink_d2;
    reg                                eop_sink_d1,eop_sink_d2,eop_sink_d3,eop_sink_d4;
    reg                                rd_ram,rd_ram_d1;
    wire                               rd_en;
    wire                               clr_stop_detect;
    wire    [1:0]                      dat_rd_hd_bit_ram;
    wire                               eff_adr_flag;//effective address flag
    reg                                eff_adr_flag_d1,eff_adr_flag_d2,eff_adr_flag_d3;
    reg     [11:0]                     adr_rd_int_ram_d1,adr_rd_int_ram_d2,adr_rd_int_ram_d3,
                                       dat_rd_deint_ram_d1,dat_rd_deint_ram_d2;
    reg                                wr_ping_pong_flag_d3,wr_ping_pong_flag_d2,wr_ping_pong_flag_d1;

    reg     [3:0]                      detect_state_current;
    reg     [3:0]                      detect_state_next;
    
    reg     [7:0]                      counter_mod_winsize_wr;
    reg     [7:0]                      counter_mod_winsize_rd;

    //*************************************************************************
    //iteration stopping rule:
    //  current half iteration hard-decision result is the same as previous half iteration
    //      or
    //  reach allowed maximum iteration number
    //*************************************************************************

    //instantiate hd_bit_ping_pong_ram
    //dpram parameters: 2-b x 8192, no output register, single clock, wr_port_width=rd_port_width
    //
    //implementing ping-pong buffer with different address space in a dpram.
    //
    //in ping/pong ram,
    //writing data with sequential incremental address,
    //reading data need perform interleaving/deinterleaving operation, so reading data
    //with corresponding interleaving/deinterleaving address is necessary.
    hd_bit_ping_pong_ram    hd_bit_ping_pong_ram
    (
        .clock      (clk_sys          ),
        .data       (d                ),
        .rdaddress  (hd_bit_ram_rd_adr),
        .rden       (rd_ram_d1        ),
        .wraddress  (hd_bit_ram_wr_adr),
        .wren       (val_sink         ),
        .q          (dat_rd_hd_bit_ram)
    );

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            counter_mod_winsize_wr <= WIN_SIZE-1'd1;
        else if( val_sink )
            if( counter_mod_winsize_wr==8'd0 )
                counter_mod_winsize_wr <= WIN_SIZE-1'd1;
            else
                counter_mod_winsize_wr <= counter_mod_winsize_wr-1'd1;
        else
            counter_mod_winsize_wr <= WIN_SIZE-1'd1;
    end

    //generate hd_bit_ram_wr_adr according to packet_length parameter
    // implementing ping-pong buffer with different address space in a dpram.
    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            wr_ram_adr_counter <= WIN_SIZE-1'd1;
        else if( val_sink )
            if( counter_mod_winsize_wr==8'd0 )
                wr_ram_adr_counter <= wr_ram_adr_counter+WIN_SIZE*2'd2-1'd1;
            else
                wr_ram_adr_counter <= wr_ram_adr_counter-1'd1;
        else
            wr_ram_adr_counter <= WIN_SIZE-1'd1;
    end

    //hd_bit_ram_wr_adr selection:
    always @ ( * ) begin
        case( wr_ping_pong_flag )
            1'b0:
                hd_bit_ram_wr_adr = wr_ram_adr_counter;
            1'b1:
                hd_bit_ram_wr_adr = wr_ram_adr_counter + 13'd4096;
            default:
                hd_bit_ram_wr_adr = 1'b0;
        endcase
    end
    //wr_ping_pong_flag: current write ping/pong flag
    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            wr_ping_pong_flag <= 1'b0;
        else if( clr_stop_detect )
            wr_ping_pong_flag <= 1'b0;
        else if( !val_sink && val_sink_d1 )
            wr_ping_pong_flag <= ~wr_ping_pong_flag;
        else
            wr_ping_pong_flag <= wr_ping_pong_flag;
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin
        if( !rst_b )
            counter_mod_winsize_rd <= WIN_SIZE-1'd1;
        else if( rd_en )
            if( counter_mod_winsize_rd==8'd0 )
                counter_mod_winsize_rd <= WIN_SIZE-1'd1;
            else
                counter_mod_winsize_rd <= counter_mod_winsize_rd-1'd1;
        else
            counter_mod_winsize_rd <= WIN_SIZE-1'd1;
    end

    always @ ( posedge clk_sys or negedge rst_b ) begin