block_cir_buf.v

上传的是WIMAX系统中

//generate output_selector1(for beta0 cal): 11->10->01->00->11
always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            output_selector1 <= 2'b01;
        else
            if( clr_cir_buf )
                output_selector1 <= 2'b01;
            else if( cir_buf_cell_wr_adr==(WIN_SIZE-1) )
                case( output_selector1 )
                    2'b00:
                        output_selector1 <= 2'b11;
                    2'b01:
                        output_selector1 <= 2'b00;
                    2'b10:
                        output_selector1 <= 2'b01;
                    2'b11:
                        output_selector1 <= 2'b10;
                    default:
                        output_selector1 <= 2'b11;
                endcase
            else
                output_selector1 <= output_selector1;
    end

//generate output_selector2(for beta1 cal): 11->10->01->00->11
always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            output_selector2 <= 2'b11;
        else
            if( clr_cir_buf )
                output_selector2 <= 2'b11;
            else if( cir_buf_cell_wr_adr==(WIN_SIZE-1) )
                case( output_selector2 )
                    2'b00:
                        output_selector2 <= 2'b11;
                    2'b01:
                        output_selector2 <= 2'b00;
                    2'b10:
                        output_selector2 <= 2'b01;
                    2'b11:
                        output_selector2 <= 2'b10;
                    default:
                        output_selector2 <= 2'b01;
                endcase
            else
                output_selector2 <= output_selector2;
    end

always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            begin
                output_selector0_d1 <= 2'b00;
                output_selector1_d1 <= 2'b00;
                output_selector2_d1 <= 2'b00;
            end
        else
            begin
                output_selector0_d1 <= output_selector0;
                output_selector1_d1 <= output_selector1;
                output_selector2_d1 <= output_selector2;
            end
    end


//*************************************************************************
//output data mux
//*************************************************************************

//output data mux according to output_selector0_d1
always @ ( * )
    begin
        case( {output_selector2==2'b00,output_selector1==2'b00,output_selector0==2'b00} )
            3'b001:
                begin
                    cir_buf_cell_rd0 = rd_cir_buf_cell0;
                    cir_buf_cell_rd_adr0 = forward_adr;
                end
            3'b010:
                begin
                    cir_buf_cell_rd0 = rd_cir_buf_cell1;
                    cir_buf_cell_rd_adr0 = backward_adr;
                end
            3'b100:
                begin
                    cir_buf_cell_rd0 = rd_cir_buf_cell2;
                    cir_buf_cell_rd_adr0 = backward_adr;
                end
            default:
                begin
                    cir_buf_cell_rd0 = 1'b0;
                    cir_buf_cell_rd_adr0 = 1'b0;
                end
        endcase
    end

always @ ( * )
    begin
        case( {output_selector2==2'b01,output_selector1==2'b01,output_selector0==2'b01} )
            3'b001:
                begin
                    cir_buf_cell_rd1 = rd_cir_buf_cell0;
                    cir_buf_cell_rd_adr1 = forward_adr;
                end
            3'b010:
                begin
                    cir_buf_cell_rd1 = rd_cir_buf_cell1;
                    cir_buf_cell_rd_adr1 = backward_adr;
                end
            3'b100:
                begin
                    cir_buf_cell_rd1 = rd_cir_buf_cell2;
                    cir_buf_cell_rd_adr1 = backward_adr;
                end
            default:
                begin
                    cir_buf_cell_rd1 = 1'b0;
                    cir_buf_cell_rd_adr1 = 1'b0;
                end
        endcase
    end

always @ ( * )
    begin
        case( {output_selector2==2'b10,output_selector1==2'b10,output_selector0==2'b10} )
            3'b001:
                begin
                    cir_buf_cell_rd2 = rd_cir_buf_cell0;
                    cir_buf_cell_rd_adr2 = forward_adr;
                end
            3'b010:
                begin
                    cir_buf_cell_rd2 = rd_cir_buf_cell1;
                    cir_buf_cell_rd_adr2 = backward_adr;
                end
            3'b100:
                begin
                    cir_buf_cell_rd2 = rd_cir_buf_cell2;
                    cir_buf_cell_rd_adr2 = backward_adr;
                end
            default:
                begin
                    cir_buf_cell_rd2 = 1'b0;
                    cir_buf_cell_rd_adr2 = 1'b0;
                end
        endcase
    end

always @ ( * )
    begin
        case( {output_selector2==2'b11,output_selector1==2'b11,output_selector0==2'b11} )
            3'b001:
                begin
                    cir_buf_cell_rd3 = rd_cir_buf_cell0;
                    cir_buf_cell_rd_adr3 = forward_adr;
                end
            3'b010:
                begin
                    cir_buf_cell_rd3 = rd_cir_buf_cell1;
                    cir_buf_cell_rd_adr3 = backward_adr;
                end
            3'b100:
                begin
                    cir_buf_cell_rd3 = rd_cir_buf_cell2;
                    cir_buf_cell_rd_adr3 = backward_adr;
                end
            default:
                begin
                    cir_buf_cell_rd3 = 1'b0;
                    cir_buf_cell_rd_adr3 = 1'b0;
                end
        endcase
    end


//*************************************************************************
//output_dat select
//*************************************************************************

//output_dat0 select
always @ ( * )
    case( output_selector0_d1 )
        2'b00:
            begin
                output_dat0 = cir_buf_cell_rd_dat0;
            end
        2'b01:
            begin
                output_dat0 = cir_buf_cell_rd_dat1;
            end
        2'b10:
            begin
                output_dat0 = cir_buf_cell_rd_dat2;
            end
        2'b11:
            begin
                output_dat0 = cir_buf_cell_rd_dat3;
            end
        default:
            begin
                output_dat0 = cir_buf_cell_rd_dat0;
            end
    endcase

//output_dat1 select
always @ ( * )
    case( output_selector1_d1 )
        2'b00:
            begin
                output_dat1 = cir_buf_cell_rd_dat0;
            end
        2'b01:
            begin
                output_dat1 = cir_buf_cell_rd_dat1;
            end
        2'b10:
            begin
                output_dat1 = cir_buf_cell_rd_dat2;
            end
        2'b11:
            begin
                output_dat1 = cir_buf_cell_rd_dat3;
            end
        default:
            begin
                output_dat1 = cir_buf_cell_rd_dat0;
            end
    endcase

//output_dat2 select
always @ ( * )
    case( output_selector2_d1 )
        2'b00:
            begin
                output_dat2 = cir_buf_cell_rd_dat0;
            end
        2'b01:
            begin
                output_dat2 = cir_buf_cell_rd_dat1;
            end
        2'b10:
            begin
                output_dat2 = cir_buf_cell_rd_dat2;
            end
        2'b11:
            begin
                output_dat2 = cir_buf_cell_rd_dat3;
            end
        default:
            begin
                output_dat2 = cir_buf_cell_rd_dat0;
            end
    endcase


endmodule   ///block_cir_buf