block_cir_buf.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : block_cir_buf.v
/// Author       : yuanliuqing
/// Department   : WiMAX department
/// Email        : [e-mail]
///
/// Module_name  : block_cir_buf
/// Called by    : max_log_map  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
///                   |----block_cir_buf_cell0
///                   |----block_cir_buf_cell1
/// block_cir_buf-----|----block_cir_buf_cell2
///                   |----block_cir_buf_cell3
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-17  | 建立文件
/// 1.0-1       | 2007-12-21  | 修改格式
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核alpha计算、beta计算循环缓冲结构
///*********************************************************************

`timescale 1ns/100ps

module block_cir_buf
    #(parameter SOFT_INFO_WIDTH  = 6'd6,                ///软信息数据宽度
                PRIOR_INFO_WIDTH = 6'd8,                ///先验信息数据款度
                WIN_SIZE         = 6'd32,               ///sliding window size, unit: lattice
                CIR_BUF_ADR_SIZE = 6'd6     )           ///sliding window size, unit: lattice
    (
    ///system i/f
    input              clk_sys,                         ///系统时钟信号
    input              rst_b,                           ///输入复位信号
    ///input i/f
    input   [SOFT_INFO_WIDTH*2-1:0]     ys,             ///soft info: system part
    input   [SOFT_INFO_WIDTH*2-1:0]     yp,             ///soft info: check part
    input   [PRIOR_INFO_WIDTH*3-1:0]    la,             ///prior info
    input                               sop_source,     ///start of source packet(not window)
    input                               eop_source,     ///end of source packet(not window)
    input                               val_source,     ///source data valid
    input                               clr_cir_buf,
    ///output i/f
    input                               rd_cir_buf_cell0,
    input                               rd_cir_buf_cell1,
    input                               rd_cir_buf_cell2,
    output reg [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] output_dat0,
    output reg [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] output_dat1,
    output reg [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] output_dat2
    );

///*********************************************************************
///内部信号定义
///*********************************************************************
reg                                             cir_buf_cell_wr0;
reg                                             cir_buf_cell_wr1;
reg                                             cir_buf_cell_wr2;
reg                                             cir_buf_cell_wr3;
reg                                             cir_buf_cell_rd0;
reg                                             cir_buf_cell_rd1;
reg                                             cir_buf_cell_rd2;
reg                                             cir_buf_cell_rd3;
wire [CIR_BUF_ADR_SIZE-1:0]                     cir_buf_cell_wr_adr;
reg  [CIR_BUF_ADR_SIZE-1:0]                     cir_buf_cell_rd_adr0;
reg  [CIR_BUF_ADR_SIZE-1:0]                     cir_buf_cell_rd_adr1;
reg  [CIR_BUF_ADR_SIZE-1:0]                     cir_buf_cell_rd_adr2;
reg  [CIR_BUF_ADR_SIZE-1:0]                     cir_buf_cell_rd_adr3;
wire [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] cir_buf_cell_rd_dat0;
wire [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] cir_buf_cell_rd_dat1;
wire [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] cir_buf_cell_rd_dat2;
wire [PRIOR_INFO_WIDTH*3+SOFT_INFO_WIDTH*4-1:0] cir_buf_cell_rd_dat3;

reg  [CIR_BUF_ADR_SIZE-1:0]                     forward_adr;    ///incremental adr for wr/rd circular_buffer_cell
reg  [CIR_BUF_ADR_SIZE-1:0]                     backward_adr;   ///decreasing adr for rd circular_buffer_cell


///*************************************************************************
///block circular ram array: including 4 circular_buffer_cell
///*************************************************************************

///instantiate block_cir_buf_cell0
///dpram parameters: 48-b x 64, no output register, singal clock, wr_port_width=rd_port_width
block_cir_buf_cell block_cir_buf_cell0
(
    .clock      (clk_sys             ),
    .data       ({la,yp,ys}          ),
    .rdaddress  (cir_buf_cell_rd_adr0),
    .rden       (cir_buf_cell_rd0    ),
    .wraddress  (cir_buf_cell_wr_adr ),
    .wren       (cir_buf_cell_wr0    ),
    .q          (cir_buf_cell_rd_dat0)
    );

///instantiate block_cir_buf_cell1
///dpram parameters: 48-b x 64, no output register, singal clock, wr_port_width=rd_port_width
block_cir_buf_cell block_cir_buf_cell1
(
    .clock      (clk_sys             ),
    .data       ({la,yp,ys}          ),
    .rdaddress  (cir_buf_cell_rd_adr1),
    .rden       (cir_buf_cell_rd1    ),
    .wraddress  (cir_buf_cell_wr_adr ),
    .wren       (cir_buf_cell_wr1    ),
    .q          (cir_buf_cell_rd_dat1)
    );

///instantiate block_cir_buf_cell2
///dpram parameters: 48-b x 64, no output register, singal clock, wr_port_width=rd_port_width
block_cir_buf_cell block_cir_buf_cell2
(
    .clock      (clk_sys             ),
    .data       ({la,yp,ys}          ),
    .rdaddress  (cir_buf_cell_rd_adr2),
    .rden       (cir_buf_cell_rd2    ),
    .wraddress  (cir_buf_cell_wr_adr ),
    .wren       (cir_buf_cell_wr2    ),
    .q          (cir_buf_cell_rd_dat2)
    );

///instantiate block_cir_buf_cell3
///dpram parameters: 48-b x 64, no output register, singal clock, wr_port_width=rd_port_width
block_cir_buf_cell block_cir_buf_cell3
(
    .clock      (clk_sys             ),
    .data       ({la,yp,ys}          ),
    .rdaddress  (cir_buf_cell_rd_adr3),
    .rden       (cir_buf_cell_rd3    ),
    .wraddress  (cir_buf_cell_wr_adr ),
    .wren       (cir_buf_cell_wr3    ),
    .q          (cir_buf_cell_rd_dat3)
    );


///*************************************************************************
///block circular ram array rd/wr signals generation
///*************************************************************************

assign cir_buf_cell_wr_adr = forward_adr;

//generate forward_adr according to WIN_SIZE parameter
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        forward_adr <= 1'b0;
    else if( clr_cir_buf )
        forward_adr <= 1'b0;
    else if( val_source || rd_cir_buf_cell0 ) begin
        if( forward_adr<(WIN_SIZE-1) )
            forward_adr <= forward_adr + 1'b1;
        else
            forward_adr <= 1'b0;
    end
    else
        forward_adr <= forward_adr;
end

///generate backward_adr according to WIN_SIZE parameter
always @ ( posedge clk_sys or negedge rst_b ) begin
    if( !rst_b )
        backward_adr <= WIN_SIZE-1'b1;
    else if( clr_cir_buf )
        backward_adr <= WIN_SIZE-1'b1;
    else if( rd_cir_buf_cell1 || rd_cir_buf_cell2 ) begin
        if( backward_adr>0 )
            backward_adr <= backward_adr - 1'b1;
        else
            backward_adr <= WIN_SIZE-1'b1;
    end
    else
        backward_adr <= backward_adr;
end

reg [1:0] input_selector;
//generate input_selector: 00->01->10->11->00
always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            begin
                input_selector <= 1'b0;
            end
        else
            begin
                if( clr_cir_buf )
                    input_selector <= 1'b0;
                else if( cir_buf_cell_wr_adr==(WIN_SIZE-1) && val_source )
                    input_selector <= input_selector + 1'b1;
                else
                    input_selector <= input_selector;
            end

    end

//input data mux according to input_selector
always @ ( * )
    case( input_selector )
        2'b00:
            begin
                cir_buf_cell_wr0 = val_source;
                cir_buf_cell_wr1 = 1'b0;
                cir_buf_cell_wr2 = 1'b0;
                cir_buf_cell_wr3 = 1'b0;
            end
        2'b01:
            begin
                cir_buf_cell_wr0 = 1'b0;
                cir_buf_cell_wr1 = val_source;
                cir_buf_cell_wr2 = 1'b0;
                cir_buf_cell_wr3 = 1'b0;
            end
        2'b10:
            begin
                cir_buf_cell_wr0 = 1'b0;
                cir_buf_cell_wr1 = 1'b0;
                cir_buf_cell_wr2 = val_source;
                cir_buf_cell_wr3 = 1'b0;
            end
        2'b11:
            begin
                cir_buf_cell_wr0 = 1'b0;
                cir_buf_cell_wr1 = 1'b0;
                cir_buf_cell_wr2 = 1'b0;
                cir_buf_cell_wr3 = val_source;
            end
        default:
            begin
                cir_buf_cell_wr0 = val_source;
                cir_buf_cell_wr1 = 1'b0;
                cir_buf_cell_wr2 = 1'b0;
                cir_buf_cell_wr3 = 1'b0;
            end
    endcase

//block circular ram array output selector
reg [1:0] output_selector0;
reg [1:0] output_selector0_d1;

reg [1:0] output_selector1;
reg [1:0] output_selector1_d1;

reg [1:0] output_selector2;
reg [1:0] output_selector2_d1;
//generate output_selector0(for alpha cal): 00->01->10->11->00
always @ ( posedge clk_sys or negedge rst_b )
    begin
        if( !rst_b )
            output_selector0 <= 2'b10;
        else
            if( clr_cir_buf )
                output_selector0 <= 2'b10;
            else if( cir_buf_cell_wr_adr==(WIN_SIZE-1) )
                output_selector0 <= output_selector0 + 1'b1;
            else
                output_selector0 <= output_selector0;
    end