ctc_rx_fsm.v

上传的是WIMAX系统中

        end
        else begin
            dpram21_wr    <= 1'b0;
            dpram21_wradr <= dpram21_wradr;
            dpram21_wrdat <= dpram21_wrdat;
            dpram22_wr    <= 1'b0;
            dpram22_wradr <= dpram22_wradr;
            dpram22_wrdat <= dpram22_wrdat;
        end
        temp2 <= {dat_rd_proc,temp2[95:32]};
    end
    else begin
        dpram21_wr    <= 1'b0;
        dpram21_wradr <= dpram21_wradr;
        dpram21_wrdat <= dpram21_wrdat;
        dpram22_wr    <= 1'b0;
        dpram22_wradr <= dpram22_wradr;
        dpram22_wrdat <= dpram22_wrdat;
    end
end  //

    //生成ctc_dpram_3的写接口信号
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b) begin
        dpram31_wr    <= 1'b0;
        dpram31_wradr <= 11'h7ff;
        dpram31_wrdat <= 24'b0;
        dpram32_wr    <= 1'b0;
        dpram32_wradr <= 11'h7ff;
        dpram32_wrdat <= 48'b0;
                temp3 <= 96'b0;
    end
    else if(st_current==IDLE) begin
        dpram31_wr    <= 1'b0;
        dpram31_wradr <= 11'h7ff;
        dpram31_wrdat <= 24'b0;
        dpram32_wr    <= 1'b0;
        dpram32_wradr <= 11'h7ff;
        dpram32_wrdat <= 48'b0;
    end
    else if((st_next==WR_SRG3) | (st_current==WR_SRG3)) begin
        if(r3_cnt==2'b10) begin
            dpram31_wr    <= 1'b1;
            dpram31_wrdat <= {temp3[63:58],temp3[55:50],temp3[15:10],temp3[7:2]};
            dpram31_wradr <= dpram31_wradr + 11'b1;
            dpram32_wr    <= 1'b1;
            dpram32_wrdat <= {temp3[95:90],temp3[87:82],temp3[79:74],temp3[71:66],
                              temp3[47:42],temp3[39:34],temp3[31:26],temp3[23:18]};
            dpram32_wradr <= dpram32_wradr + 11'b1;
        end
        else begin
            dpram31_wr    <= 1'b0;
            dpram31_wradr <= dpram31_wradr;
            dpram31_wrdat <= dpram31_wrdat;
            dpram32_wr    <= 1'b0;
            dpram32_wradr <= dpram32_wradr;
            dpram32_wrdat <= dpram32_wrdat;
        end
        temp3 <= {dat_rd_proc,temp3[95:32]};
    end
    else begin
        dpram31_wr    <= 1'b0;
        dpram31_wradr <= dpram31_wradr;
        dpram31_wrdat <= dpram31_wrdat;
        dpram32_wr    <= 1'b0;
        dpram32_wradr <= dpram32_wradr;
        dpram32_wrdat <= dpram32_wrdat;
    end
end  //

ctc_rx_arb ctc_rx_arb 
(
    .core1_req      (core1_req      ),
    .core1_gnt      (core1_gnt      ),
    .core2_req      (core2_req      ),
    .core2_gnt      (core2_gnt      ),
    .core3_req      (core3_req      ),
    .core3_gnt      (core3_gnt      ),
    .p_len          (p_len          ),
    .empty          (empty          ),
    .wr1_over       (wr1_over       ),
    .wr2_over       (wr2_over       ),
    .wr3_over       (wr3_over       ),
    .ctc_fifo1_usedw(ctc_fifo1_usedw),
    .ctc_fifo2_usedw(ctc_fifo2_usedw),
    .ctc_fifo3_usedw(ctc_fifo3_usedw),
    .sys_clk        (sys_clk        ),
    .reset_b        (reset_b        )
);
///**************************************************************************
///生成wr1_over信号
///生成wr2_over信号
///生成wr3_over信号
///**************************************************************************
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        wr1_over <= 1'b0;
    else if((st_current==W_SRG1) & (r11_cnt_next==(p_len>>2)))
        wr1_over <= 1'b1;
    else
        wr1_over <= 1'b0;
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        wr2_over <= 1'b0;
    else if((st_current==WR_SRG2) & (r22_cnt_next==(p_len>>2)))
        wr2_over <= 1'b1;
    else
        wr2_over <= 1'b0;
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        wr3_over <= 1'b0;
    else if((st_current==WR_SRG3) & (r33_cnt_next==(p_len>>2)))
        wr3_over <= 1'b1;
    else
        wr3_over <= 1'b0;
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        p_len <= 16'b0;
    else if(st_current==WT1)
        p_len <= dat_rd[15:0];
    else
        p_len <= p_len;
end
///**************************************************************************
///原先是6cycle除法，现改成12cycle，增加了6cycle
///因为除法的结果要等到wr_over信号有效时才使用，故增加不影响整体结果
///**************************************************************************
div div_inst 
(
    .clock    ( sys_clk    ),
    .denom    ( 16'd6      ),
    .numer    ( p_len      ),
    .quotient ( p_len_next ),
    .remain   (            )
);



   assign  rx2ctrl1_length_next = p_len_next;
   assign  rx2ctrl2_length_next = p_len_next;
   assign  rx2ctrl3_length_next = p_len_next;

always @(*) begin
    rx2ctrl1_type_next           = rx2ctrl1_type;
    rx2ctrl1_frame_end_flag_next = rx2ctrl1_frame_end_flag;   //add by mahui 070704
    rx2ctrl1_inst_next           = rx2ctrl1_inst;
    rx2ctrl1_code_rate_next      = rx2ctrl1_code_rate;
    rx2ctrl1_modu_type_next      = rx2ctrl1_modu_type;
    rx2ctrl1_bnum_next           = rx2ctrl1_bnum;
    rx2ctrl1_fnum_next           = rx2ctrl1_fnum;
    rx2ctrl1_miter_next          = rx2ctrl1_miter;
    rx2ctrl1_segId_next          = rx2ctrl1_segId; //Segment ID  add by mahui 070704
    rx2ctrl2_type_next           = rx2ctrl2_type;
    rx2ctrl2_frame_end_flag_next = rx2ctrl2_frame_end_flag;   //add by mahui 070704
    rx2ctrl2_inst_next           = rx2ctrl2_inst;
    rx2ctrl2_code_rate_next      = rx2ctrl2_code_rate;
    rx2ctrl2_modu_type_next      = rx2ctrl2_modu_type;
    rx2ctrl2_bnum_next           = rx2ctrl2_bnum;
    rx2ctrl2_fnum_next           = rx2ctrl2_fnum;
    rx2ctrl2_miter_next          = rx2ctrl2_miter;
    rx2ctrl2_segId_next          = rx2ctrl2_segId; //Segment ID  add by mahui 070704
    rx2ctrl3_type_next           = rx2ctrl3_type;
    rx2ctrl3_frame_end_flag_next = rx2ctrl3_frame_end_flag;   //add by mahui 070704
    rx2ctrl3_inst_next           = rx2ctrl3_inst;
    rx2ctrl3_code_rate_next      = rx2ctrl3_code_rate;
    rx2ctrl3_modu_type_next      = rx2ctrl3_modu_type;
    rx2ctrl3_bnum_next           = rx2ctrl3_bnum;
    rx2ctrl3_fnum_next           = rx2ctrl3_fnum;
    rx2ctrl3_miter_next          = rx2ctrl3_miter;
    rx2ctrl3_segId_next          = rx2ctrl3_segId; //Segment ID  add by mahui 070704
    if(st_current==WT1) begin                          ///第一个字
        rx2ctrl1_type_next           = dat_rd[31:29];
        rx2ctrl1_frame_end_flag_next = dat_rd[28:26];   //add by mahui 070704
        rx2ctrl1_inst_next           = dat_rd[25:24];
        rx2ctrl1_code_rate_next      = dat_rd[23:21];
        rx2ctrl1_modu_type_next      = dat_rd[17:16];
        rx2ctrl2_type_next           = dat_rd[31:29];
        rx2ctrl2_frame_end_flag_next = dat_rd[28:26];   //add by mahui 070704
        rx2ctrl2_inst_next           = dat_rd[25:24];
        rx2ctrl2_code_rate_next      = dat_rd[23:21];
        rx2ctrl2_modu_type_next      = dat_rd[17:16];
        rx2ctrl3_type_next           = dat_rd[31:29];
        rx2ctrl3_frame_end_flag_next = dat_rd[28:26];   //add by mahui 070704
        rx2ctrl3_inst_next           = dat_rd[25:24];
        rx2ctrl3_code_rate_next      = dat_rd[23:21];
        rx2ctrl3_modu_type_next      = dat_rd[17:16];
    end
    else if(st_current==WAIT1) begin                       ///第二个字
      
        rx2ctrl1_bnum_next           = dat_rd[31:16];
        rx2ctrl1_fnum_next           = dat_rd[15:8];
        rx2ctrl1_miter_next          = dat_rd[7:4];//rev from [3:0] to [7:4]
        rx2ctrl1_segId_next          = dat_rd[3:0];    //add by mahui 070704
        rx2ctrl2_bnum_next           = dat_rd[31:16];
        rx2ctrl2_fnum_next           = dat_rd[15:8];
        rx2ctrl2_miter_next          = dat_rd[7:4];//rev from [3:0] to [7:4]
        rx2ctrl2_segId_next          = dat_rd[3:0];    //add by mahui 070704
        rx2ctrl3_bnum_next           = dat_rd[31:16];
        rx2ctrl3_fnum_next           = dat_rd[15:8];
        rx2ctrl3_miter_next          = dat_rd[7:4];//rev from [3:0] to [7:4]
        rx2ctrl3_segId_next          = dat_rd[3:0];    //add by mahui 070704
    end
end //get the output signals

    //register output signals
always @(posedge sys_clk or negedge reset_b) begin
    if(~reset_b) begin
        rx2ctrl1_length         <= 16'b0;
        rx2ctrl1_type           <= 3'b0;
        rx2ctrl1_frame_end_flag <= 3'd0;   //add by mahui 070704
        rx2ctrl1_inst           <= 2'b0;
        rx2ctrl1_code_rate      <= 3'b0;
        rx2ctrl1_modu_type      <= 2'b0;
        rx2ctrl1_bnum           <= 16'b0;
        rx2ctrl1_fnum           <= 8'b0;
        rx2ctrl1_miter          <= 4'b0;
        rx2ctrl1_segId          <= 4'd0;        //add by mahui 070704
        rx2ctrl2_length         <= 16'b0;
        rx2ctrl2_type           <= 3'b0;
        rx2ctrl2_frame_end_flag <= 3'd0;   //add by mahui 070704
        rx2ctrl2_inst           <= 2'b0;
        rx2ctrl2_code_rate      <= 3'b0;
        rx2ctrl2_modu_type      <= 2'b0;
        rx2ctrl2_bnum           <= 16'b0;
        rx2ctrl2_fnum           <= 8'b0;
        rx2ctrl2_miter          <= 4'b0;
        rx2ctrl2_segId          <= 4'd0;        //add by mahui 070704
        rx2ctrl3_length         <= 16'b0;
        rx2ctrl3_type           <= 3'b0;
        rx2ctrl3_frame_end_flag <= 3'd0;   //add by mahui 070704
        rx2ctrl3_inst           <= 2'b0;
        rx2ctrl3_code_rate      <= 3'b0;
        rx2ctrl3_modu_type      <= 2'b0;
        rx2ctrl3_bnum           <= 16'b0;
        rx2ctrl3_fnum           <= 8'b0;
        rx2ctrl3_miter          <= 4'b0;
        rx2ctrl3_segId          <= 4'd0;        //add by mahui 070704
    end
    else begin
        rx2ctrl1_length         <= rx2ctrl1_length_next;
        rx2ctrl1_type           <= rx2ctrl1_type_next;
        rx2ctrl1_frame_end_flag <= rx2ctrl1_frame_end_flag_next;   //add by mahui 070704
        rx2ctrl1_inst           <= rx2ctrl1_inst_next;
        rx2ctrl1_code_rate      <= rx2ctrl1_code_rate_next;
        rx2ctrl1_modu_type      <= rx2ctrl1_modu_type_next;
        rx2ctrl1_bnum           <= rx2ctrl1_bnum_next;
        rx2ctrl1_fnum           <= rx2ctrl1_fnum_next;
        rx2ctrl1_miter          <= rx2ctrl1_miter_next;
        rx2ctrl1_segId          <= rx2ctrl1_segId_next; //add by mahui 070704
        rx2ctrl2_length         <= rx2ctrl2_length_next;
        rx2ctrl2_type           <= rx2ctrl2_type_next;
        rx2ctrl2_frame_end_flag <= rx2ctrl2_frame_end_flag_next;   //add by mahui 070704
        rx2ctrl2_inst           <= rx2ctrl2_inst_next;
        rx2ctrl2_code_rate      <= rx2ctrl2_code_rate_next;
        rx2ctrl2_modu_type      <= rx2ctrl2_modu_type_next;
        rx2ctrl2_bnum           <= rx2ctrl2_bnum_next;
        rx2ctrl2_fnum           <= rx2ctrl2_fnum_next;
        rx2ctrl2_miter          <= rx2ctrl2_miter_next;
        rx2ctrl2_segId          <= rx2ctrl2_segId_next; //add by mahui 070704
        rx2ctrl3_length         <= rx2ctrl3_length_next;
        rx2ctrl3_type           <= rx2ctrl3_type_next;
        rx2ctrl3_frame_end_flag <= rx2ctrl3_frame_end_flag_next;   //add by mahui 070704
        rx2ctrl3_inst           <= rx2ctrl3_inst_next;
        rx2ctrl3_code_rate      <= rx2ctrl3_code_rate_next;
        rx2ctrl3_modu_type      <= rx2ctrl3_modu_type_next;
        rx2ctrl3_bnum           <= rx2ctrl3_bnum_next;
        rx2ctrl3_fnum           <= rx2ctrl3_fnum_next;
        rx2ctrl3_miter          <= rx2ctrl3_miter_next;
        rx2ctrl3_segId          <= rx2ctrl3_segId_next; //add by mahui 070704
    end
end //register output signals

endmodule  ///ctc_rx_fsm