ctc_rx_fsm.v

上传的是WIMAX系统中

        HEAD: st_next = WT1;
        WT1:  st_next = WT2;
        
        WT2: 
            if(usedw >= (p_len>>2))
                st_next = LEN;
            else
                st_next = WT2;
        
        LEN: st_next = WAIT1;
        WAIT1: st_next = WAIT2;
        
        WAIT2:
            if(core1_gnt)
                st_next = READ1;
            else if(core2_gnt)
                st_next = READ2;
            else if(core3_gnt)
                st_next = READ3;
            else
                st_next = WAIT2;
        
        READ1: st_next = W_SRG1;
        W_SRG1:
            if(r11_cnt_next < (p_len>>2))
                st_next = W_SRG1;
            else
                st_next = IDLE;
        
        READ2: st_next = WR_SRG2;
        WR_SRG2:
            if(r22_cnt_next < (p_len>>2))
                st_next = WR_SRG2;
            else
                st_next = IDLE;
        
        READ3: st_next = WR_SRG3;
        WR_SRG3:
           if(r33_cnt_next < (p_len>>2))
               st_next = WR_SRG3;
           else
               st_next = IDLE;
        default: st_next = IDLE;
    endcase
end //state machine

    //
always @(posedge sys_clk or negedge reset_b) begin
    if(~reset_b) begin
        r11_cnt <= 16'b0;
        r22_cnt <= 16'b0;
        r33_cnt <= 16'b0;
        r1_cnt  <= 2'b0;
        r2_cnt  <= 2'b0;
        r3_cnt  <= 2'b0;
    end
    else begin
        r11_cnt <= r11_cnt_next;
        r22_cnt <= r22_cnt_next;
        r33_cnt <= r33_cnt_next;
        r1_cnt  <= r1_cnt_next;
        r2_cnt  <= r2_cnt_next;
        r3_cnt  <= r3_cnt_next;
    end
end  //

      //生成长度值
always @(*) begin
    r11_cnt_next = r11_cnt;
    r22_cnt_next = r22_cnt;
    r33_cnt_next = r33_cnt;
    r1_cnt_next  = r1_cnt;
    r2_cnt_next  = r2_cnt;
    r3_cnt_next  = r3_cnt;

    if(st_current == IDLE) begin
        r11_cnt_next = 16'b0;
        r1_cnt_next  = 2'b0;
    end
    else if(st_current==W_SRG1) begin
        r11_cnt_next = r11_cnt + 1'b1;
        if(r1_cnt==2'b10)
            r1_cnt_next = 2'b0;
        else
            r1_cnt_next = r1_cnt + 1'b1;
    end

    if(st_current==IDLE) begin
        r22_cnt_next = 16'b0;
        r2_cnt_next  = 2'b0;
    end
    else if(st_current==WR_SRG2) begin
        r22_cnt_next  = r22_cnt + 1'b1;
        if(r2_cnt==2'b10)
            r2_cnt_next = 2'b0;
        else
            r2_cnt_next = r2_cnt + 1'b1;
    end

    if(st_current==IDLE) begin
        r33_cnt_next = 16'b0;
        r3_cnt_next  = 2'b0;
    end
    else if(st_current==WR_SRG3) begin
        r33_cnt_next  = r33_cnt + 1'b1;
        if(r3_cnt==2'b10)
            r3_cnt_next = 2'b0;
        else
            r3_cnt_next = r3_cnt + 1'b1;
    end
end //get the output signals



    //生成FIFO接口信号
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        rd <= 1'b0;
    else
        case(st_next)
            HEAD: rd <= 1'b1;
            LEN:
                if(!empty)
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            WAIT1:
                if(!empty)
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            READ1:
                if(!empty)
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            W_SRG1:
                if(!empty & (r11_cnt_next < ((p_len>>2)-16'h2)))
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            READ2:
                if(!empty)
                    rd <= 1'b1;
                else   
                    rd <= 1'b0;
            WR_SRG2:
                if(!empty & (r22_cnt_next < ((p_len>>2)-16'h2)))
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            READ3:
                if(!empty)
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            WR_SRG3:
                if(!empty & (r33_cnt_next < ((p_len>>2)-16'h2)))
                    rd <= 1'b1;
                else
                    rd <= 1'b0;
            default:
                rd <= 1'b0;
        endcase
end

        //*********** add by yuanlq 2006.11.23
reg     [31:0]  dat_rd_proc;//saturate 8-bx4 to {6-b,2'b00}x4
always@(*) begin
                                                         //[7:0]
    if(8'd31<dat_rd[7:0] && dat_rd[7:0]<8'd128)          //positive saturation, 31
        dat_rd_proc[7:0] = {6'd31,2'b00};                //0111_1100
    else if(8'd127<dat_rd[7:0] && dat_rd[7:0]<8'd224)    //negative saturation, -32
        dat_rd_proc[7:0] = {6'd32,2'b00};                //1000_0000
    else                                                 //no saturation
        dat_rd_proc[7:0] = {dat_rd[5:0],2'b00};          
                                                         //[15:8]
    if(8'd31<dat_rd[15:8] && dat_rd[15:8]<8'd128)        //positive saturation, 31
        dat_rd_proc[15:8] = {6'd31,2'b00};               
    else if(8'd127<dat_rd[15:8] && dat_rd[15:8]<8'd224)  //negative saturation, -32
        dat_rd_proc[15:8] = {6'd32,2'b00};               
    else                                                 //no saturation
        dat_rd_proc[15:8] = {dat_rd[13:8],2'b00};        
                                                         //[23:16]
    if(8'd31<dat_rd[23:16] && dat_rd[23:16]<8'd128)      //positive saturation, 31
        dat_rd_proc[23:16] = {6'd31,2'b00};
    else if(8'd127<dat_rd[23:16] && dat_rd[23:16]<8'd224)//negative saturation, -32
        dat_rd_proc[23:16] = {6'd32,2'b00};
    else                                                 //no saturation
        dat_rd_proc[23:16] = {dat_rd[21:16],2'b00};
                                                         //[31:24]
    if(8'd31<dat_rd[31:24] && dat_rd[31:24]<8'd128)      //positive saturation, 31
        dat_rd_proc[31:24] = {6'd31,2'b00};
    else if(8'd127<dat_rd[31:24] && dat_rd[31:24]<8'd224)//negative saturation, -32
        dat_rd_proc[31:24] = {6'd32,2'b00};
    else                                                 //no saturation
        dat_rd_proc[31:24] = {dat_rd[29:24],2'b00};
end
//**************

reg  [95:0]  temp1;
reg  [95:0]  temp2;
reg  [95:0]  temp3;
//生成ctc_dpram_1的写接口信号
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b) begin
        dpram11_wr    <= 1'b0;
        dpram11_wradr <= 11'h7ff;
        dpram11_wrdat <= 24'b0;
        dpram12_wr    <= 1'b0;
        dpram12_wradr <= 11'h7ff;
        dpram12_wrdat <= 48'b0;
                temp1 <= 96'b0;
    end
    else if(st_current==IDLE) begin
        dpram11_wr    <= 1'b0;
        dpram11_wradr <= 11'h7ff;
        dpram11_wrdat <= 24'b0;
        dpram12_wr    <= 1'b0;
        dpram12_wradr <= 11'h7ff;
        dpram12_wrdat <= 48'b0;
    end
    else if((st_next==W_SRG1) || (st_current==W_SRG1)) begin
        if(r1_cnt==2'b10) begin  ///凑齐96比特再赋值
            dpram11_wr    <= 1'b1;
            dpram11_wrdat <= {temp1[63:58],temp1[55:50],temp1[15:10],temp1[7:2]};
            dpram11_wradr <= dpram11_wradr + 11'b1;  //dpram11_wradr=000_0000_0000
            dpram12_wr    <= 1'b1;
            dpram12_wrdat <= {temp1[95:90],temp1[87:82],temp1[79:74],temp1[71:66],
                              temp1[47:42],temp1[39:34],temp1[31:26],temp1[23:18]};
            dpram12_wradr <= dpram12_wradr + 11'b1;
        end
        else begin
            dpram11_wr    <= 1'b0;
            dpram11_wradr <= dpram11_wradr;
            dpram11_wrdat <= dpram11_wrdat;
            dpram12_wr    <= 1'b0;
            dpram12_wradr <= dpram12_wradr;
            dpram12_wrdat <= dpram12_wrdat;
       end
       temp1 <= {dat_rd_proc,temp1[95:32]};
    end
    else begin
        dpram11_wr    <= 1'b0;
        dpram11_wradr <= dpram11_wradr;
        dpram11_wrdat <= dpram11_wrdat;
        dpram12_wr    <= 1'b0;
        dpram12_wradr <= dpram12_wradr;
        dpram12_wrdat <= dpram12_wrdat;
    end
end  //

    //生成ctc_dpram_2的写接口信号
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b) begin
        dpram21_wr    <= 1'b0;
        dpram21_wradr <= 11'h7ff;
        dpram21_wrdat <= 24'b0;
        dpram22_wr    <= 1'b0;
        dpram22_wradr <= 11'h7ff;
        dpram22_wrdat <= 48'b0;
                temp2 <= 96'b0;
    end
    else if(st_current==IDLE) begin
        dpram21_wr    <= 1'b0;
        dpram21_wradr <= 11'h7ff;
        dpram21_wrdat <= 24'b0;
        dpram22_wr    <= 1'b0;
        dpram22_wradr <= 11'h7ff;
        dpram22_wrdat <= 48'b0;
    end
    else if((st_next==WR_SRG2) | (st_current==WR_SRG2)) begin
        if(r2_cnt==2'b10) begin
            dpram21_wr    <= 1'b1;
            dpram21_wrdat <= {temp2[63:58],temp2[55:50],temp2[15:10],temp2[7:2]};
            dpram21_wradr <= dpram21_wradr + 11'b1;
            dpram22_wr    <= 1'b1;
            dpram22_wrdat <= {temp2[95:90],temp2[87:82],temp2[79:74],temp2[71:66],
                              temp2[47:42],temp2[39:34],temp2[31:26],temp2[23:18]};
            dpram22_wradr <= dpram22_wradr + 11'b1;