ctc_rx_fsm.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_rx_fsm.v
/// Author       : wangjinshan  yuanliuqing
/// Department   : 2nd IC department
/// Email        : [e-mail]
///
/// Module_name  : ctc_rx_fsm
/// Called by    : ctc_decoder  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// ctc_rx_fsm-----|----ctc_rx_arb
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-09  | 建立文件
///---------------------------------------------------------------------
/// 1.1-0       | 2006-10-09  | 更改为3个译码核
///---------------------------------------------------------------------
/// Main Function:
/// 1、CTC译码核输入状态机
///*********************************************************************

`timescale 1ns/100ps

module ctc_rx_fsm
    (
    ///pre_ctc_fifo rd i/f
    input              empty,                       ///FIFO空指示信号
    input       [12:0] usedw,
    input              eop_rd,                      ///包结束信号
    input       [31:0] dat_rd,                      ///FIFO读数据
    output reg         rd,                          ///FIFO读信号

    ///interface signals with ctc_decoder_core1
    ///input
    input              core1_req,                   ///read request signal
    ///output
    output wire        core1_gnt,                   ///read grant signal
    output reg         wr1_over,                    ///写dpram1结束信号
    output reg  [15:0] rx2ctrl1_length,             ///长度
    output reg  [2:0]  rx2ctrl1_type,               ///类型号
    output reg  [1:0]  rx2ctrl1_inst,               ///instance
    output reg  [2:0]  rx2ctrl1_code_rate,          ///码率 00:1/2 01:2/3 10:3/4
    output reg  [1:0]  rx2ctrl1_modu_type,          /// 00为QPSK，01为16QAM，10为64QAM
    output reg  [15:0] rx2ctrl1_bnum,               ///突发号
    output reg  [7:0]  rx2ctrl1_fnum,               ///FEC号
    output reg  [3:0]  rx2ctrl1_miter,              ///最大迭代次数
    output reg  [3:0]  rx2ctrl1_segId,              ///segment号
    output reg  [2:0]  rx2ctrl1_frame_end_flag,     ///add by mahui 070704
    
    ///interface signals with ctc_decoder_core2
    ///input
    input              core2_req,                   ///read request signal
    ///output
    output wire        core2_gnt,                   ///read grant signal
    output reg         wr2_over,                    ///写dpram2结束信号
    output reg  [15:0] rx2ctrl2_length,             ///长度
    output reg  [2:0]  rx2ctrl2_type,               ///类型号
    output reg  [1:0]  rx2ctrl2_inst,               ///instance
    output reg  [2:0]  rx2ctrl2_code_rate,          ///码率 00:1/2 01:2/3 10:3/4
    output reg  [1:0]  rx2ctrl2_modu_type,          /// 00为QPSK，01为16QAM，10为64QAM
    output reg  [15:0] rx2ctrl2_bnum,               ///突发号
    output reg  [7:0]  rx2ctrl2_fnum,               ///FEC号
    output reg  [3:0]  rx2ctrl2_miter,              ///最大迭代次数
    output reg  [3:0]  rx2ctrl2_segId,              ///segment号
    output reg  [2:0]  rx2ctrl2_frame_end_flag,     ///add by mahui 070704

    ///interface signals with ctc_decoder_core3
    ///input
    input              core3_req,                   ///read request signal
    ///output
    output wire        core3_gnt,                   ///read grant signal
    output reg         wr3_over,                    ///写dpram3结束信号
    output reg  [15:0] rx2ctrl3_length,             ///长度
    output reg  [2:0]  rx2ctrl3_type,               ///类型号
    output reg  [1:0]  rx2ctrl3_inst,               ///instance
    output reg  [2:0]  rx2ctrl3_code_rate,          ///码率 00:1/2 01:2/3 10:3/4
    output reg  [1:0]  rx2ctrl3_modu_type,          /// 00为QPSK，01为16QAM，10为64QAM
    output reg  [15:0] rx2ctrl3_bnum,               ///突发号
    output reg  [7:0]  rx2ctrl3_fnum,               ///FEC号
    output reg  [3:0]  rx2ctrl3_miter,              ///最大迭代次数
    output reg  [3:0]  rx2ctrl3_segId,              ///segment号
    output reg  [2:0]  rx2ctrl3_frame_end_flag,     ///add by mahui 070704

    ///interface signals with ctc_dpram_11
    ///output
    output reg  [23:0] dpram11_wrdat,
    output reg         dpram11_wr,
    output reg  [10:0] dpram11_wradr,

    ///interface signals with ctc_dpram_12
    ///output
    output reg  [47:0] dpram12_wrdat,
    output reg         dpram12_wr,
    output reg  [10:0] dpram12_wradr,

    ///interface signals with ctc_dpram_21
    ///output
    output reg  [23:0] dpram21_wrdat,
    output reg         dpram21_wr,
    output reg  [10:0] dpram21_wradr,

    ///interface signals with ctc_dpram_22
    ///output
    output reg  [47:0] dpram22_wrdat,
    output reg         dpram22_wr,
    output reg  [10:0] dpram22_wradr,

    ///interface signals with ctc_dpram_31
    ///output
    output reg  [23:0] dpram31_wrdat,
    output reg         dpram31_wr,
    output reg  [10:0] dpram31_wradr,

    ///interface signals with ctc_dpram_32
    ///output
    output reg  [47:0] dpram32_wrdat,
    output reg         dpram32_wr,
    output reg  [10:0] dpram32_wradr,

    ///interface with ctc_fifo1
    ///input
    input       [8:0]  ctc_fifo1_usedw,

    ///interface with ctc_fifo2
    ///input
    input       [8:0]  ctc_fifo2_usedw,

    ///interface with ctc_fifo3
    ///input
    input       [8:0]  ctc_fifo3_usedw,

    ///system signals
    input              sys_clk,                     ///系统时钟信号
    input              reset_b,                     ///输入复位信号

    output reg  [15:0] rx_counter1_nc,
    output reg  [15:0] rx_counter2_nc,
    output reg  [15:0] rx_counter3_nc               ///************bebug code: yuanliuqing 20061120
    );

///*********************************************************************
///local parameter define：(本地参数：)
///*********************************************************************

parameter       IDLE        = 13'b0_0000_0000_0001;///!empty transit
parameter       HEAD        = 13'b0_0000_0000_0010;///read head word0,1 cycle
parameter       WT1         = 13'b0_0000_0000_0100;///get head word0,1 cycle
parameter       WT2         = 13'b0_0000_0000_1000;///WAIT2 until (usedw >= (p_len>>2))
parameter       LEN         = 13'b0_0000_0001_0000;///read head word1,1 cycle
parameter       WAIT1       = 13'b0_0000_0010_0000;///get head word1,1 cycle
parameter       WAIT2       = 13'b0_0000_0100_0000;///wait until core1_gnt or core2_gnt
parameter       READ1       = 13'b0_0000_1000_0000;///pre W_SRG1,1 cycle
parameter       W_SRG1      = 13'b0_0001_0000_0000;///W_SRG1
parameter       READ2       = 13'b0_0010_0000_0000;///pre W_SRG2,1 cycle
parameter       WR_SRG2     = 13'b0_0100_0000_0000;///W_SRG2
parameter       READ3       = 13'b0_1000_0000_0000;///pre W_SRG3,1 cycle
parameter       WR_SRG3     = 13'b1_0000_0000_0000;///W_SRG3

///*********************************************************************
///内部信号定义
///*********************************************************************

wire    [15:0]  rx2ctrl1_length_next;               ///长度
reg     [2:0]   rx2ctrl1_type_next;                 ///类型号
reg     [2:0]   rx2ctrl1_frame_end_flag_next;       ///帧结束标志    //add by mahui 070704
reg     [1:0]   rx2ctrl1_inst_next;                 ///instance
reg     [2:0]   rx2ctrl1_code_rate_next;            ///码率 00:1/2 01:2/3 10:3/4
reg     [1:0]   rx2ctrl1_modu_type_next;            /// 00为QPSK，01为16QAM，10为64QAM
reg     [15:0]  rx2ctrl1_bnum_next;                 ///突发号
reg     [7:0]   rx2ctrl1_fnum_next;                 ///FEC号
reg     [3:0]   rx2ctrl1_miter_next;                ///最大迭代次数
reg     [3:0]   rx2ctrl1_segId_next;                ///segment号

wire    [15:0]  rx2ctrl2_length_next;               ///长度
reg     [2:0]   rx2ctrl2_type_next;                 ///类型号
reg     [2:0]   rx2ctrl2_frame_end_flag_next;       ///帧结束标志    //add by mahui 070704
reg     [1:0]   rx2ctrl2_inst_next;                 ///instance
reg     [2:0]   rx2ctrl2_code_rate_next;            ///码率 00:1/2 01:2/3 10:3/4
reg     [1:0]   rx2ctrl2_modu_type_next;            /// 00为QPSK，01为16QAM，10为64QAM
reg     [15:0]  rx2ctrl2_bnum_next;                 ///突发号
reg     [7:0]   rx2ctrl2_fnum_next;                 ///FEC号
reg     [3:0]   rx2ctrl2_miter_next;                ///最大迭代次数
reg     [3:0]   rx2ctrl2_segId_next;                ///segment号

wire    [15:0]  rx2ctrl3_length_next;               ///长度
reg     [2:0]   rx2ctrl3_type_next;                 ///类型号
reg     [2:0]   rx2ctrl3_frame_end_flag_next;       ///帧结束标志    //add by mahui 070704
reg     [1:0]   rx2ctrl3_inst_next;                 ///instance
reg     [2:0]   rx2ctrl3_code_rate_next;            ///码率 00:1/2 01:2/3 10:3/4
reg     [1:0]   rx2ctrl3_modu_type_next;            /// 00为QPSK，01为16QAM，10为64QAM
reg     [15:0]  rx2ctrl3_bnum_next;                 ///突发号
reg     [7:0]   rx2ctrl3_fnum_next;                 ///FEC号
reg     [3:0]   rx2ctrl3_miter_next;                ///最大迭代次数
reg     [3:0]   rx2ctrl3_segId_next;                ///segment号

reg     [12:0]   st_current;
reg     [12:0]   st_next;

reg     [15:0]  r11_cnt;
reg     [15:0]  r22_cnt;
reg     [15:0]  r33_cnt;
reg     [15:0]  r11_cnt_next;
reg     [15:0]  r22_cnt_next;
reg     [15:0]  r33_cnt_next;
reg     [1:0]   r1_cnt;
reg     [1:0]   r2_cnt;
reg     [1:0]   r3_cnt;
reg     [1:0]   r1_cnt_next;
reg     [1:0]   r2_cnt_next;
reg     [1:0]   r3_cnt_next;

reg     [15:0]  p_len;                              ///长度,unit: soft-info,8
wire    [15:0]  p_len_next;                         ///长度,unit: lattice, 2-b

///*********************************************************************
///主程序代码：
///*********************************************************************
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        rx_counter1_nc <= 1'b0;
    else
    begin
        if(st_current==READ1)
            rx_counter1_nc <= rx_counter1_nc + 1'b1;
        else
            rx_counter1_nc <= rx_counter1_nc;
    end
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        rx_counter2_nc <= 1'b0;
    else
    begin
        if(st_current==READ2)
            rx_counter2_nc <= rx_counter2_nc + 1'b1;
        else
            rx_counter2_nc <= rx_counter2_nc;
    end
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        rx_counter3_nc <= 1'b0;
    else
    begin
        if(st_current==READ3)
            rx_counter3_nc <= rx_counter3_nc + 1'b1;
        else
            rx_counter3_nc <= rx_counter3_nc;
    end
end


// Current State Logic (sequential)
// state_intialization
always @(posedge sys_clk or negedge reset_b) begin
    if(~reset_b)
        st_current <= IDLE;
    else
        st_current <= st_next;
end  // state machine

always @(*) begin
    st_next = st_current;
    case(st_current)
        IDLE: 
            if(!empty)
                st_next = HEAD;
            else
                st_next = IDLE;