_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity pre_vit_fifo is
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        full            : out    vl_logic;
        wr              : in     vl_logic;
        eop_wr          : in     vl_logic;
        dat_wr          : in     vl_logic_vector(31 downto 0);
        empty           : out    vl_logic;
        rd              : in     vl_logic;
        eop_rd          : out    vl_logic;
        dat_rd          : out    vl_logic_vector(31 downto 0)
    );
end pre_vit_fifo;