_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_4 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha42_11      : in     vl_logic;
        alpha42_10      : in     vl_logic;
        alpha42_9       : in     vl_logic;
        alpha42_8       : in     vl_logic;
        alpha42_7       : in     vl_logic;
        alpha42_6       : in     vl_logic;
        alpha42_5       : in     vl_logic;
        alpha42_4       : in     vl_logic;
        alpha42_3       : in     vl_logic;
        alpha42_2       : in     vl_logic;
        alpha42_1       : in     vl_logic;
        alpha42_0       : in     vl_logic;
        alpha43_11      : in     vl_logic;
        alpha43_10      : in     vl_logic;
        alpha43_9       : in     vl_logic;
        alpha43_8       : in     vl_logic;
        alpha43_7       : in     vl_logic;
        alpha43_6       : in     vl_logic;
        alpha43_5       : in     vl_logic;
        alpha43_4       : in     vl_logic;
        alpha43_3       : in     vl_logic;
        alpha43_2       : in     vl_logic;
        alpha43_1       : in     vl_logic;
        alpha43_0       : in     vl_logic;
        alpha41_11      : in     vl_logic;
        alpha41_10      : in     vl_logic;
        alpha41_9       : in     vl_logic;
        alpha41_8       : in     vl_logic;
        alpha41_7       : in     vl_logic;
        alpha41_6       : in     vl_logic;
        alpha41_5       : in     vl_logic;
        alpha41_4       : in     vl_logic;
        alpha41_3       : in     vl_logic;
        alpha41_2       : in     vl_logic;
        alpha41_1       : in     vl_logic;
        alpha41_0       : in     vl_logic;
        alpha40_11      : in     vl_logic;
        alpha40_10      : in     vl_logic;
        alpha40_9       : in     vl_logic;
        alpha40_8       : in     vl_logic;
        alpha40_7       : in     vl_logic;
        alpha40_6       : in     vl_logic;
        alpha40_5       : in     vl_logic;
        alpha40_4       : in     vl_logic;
        alpha40_3       : in     vl_logic;
        alpha40_2       : in     vl_logic;
        alpha40_1       : in     vl_logic;
        alpha40_0       : in     vl_logic;
        alpha_t4_11     : out    vl_logic;
        alpha_t4_10     : out    vl_logic;
        alpha_t4_9      : out    vl_logic;
        alpha_t4_8      : out    vl_logic;
        alpha_t4_7      : out    vl_logic;
        alpha_t4_6      : out    vl_logic;
        alpha_t4_5      : out    vl_logic;
        alpha_t4_4      : out    vl_logic;
        alpha_t4_3      : out    vl_logic;
        alpha_t4_2      : out    vl_logic;
        alpha_t4_1      : out    vl_logic;
        alpha_t4_0      : out    vl_logic;
        G_103_combout   : in     vl_logic
    );
end mod_max4_a_4;