📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity beta_cal is generic( SOFT_INFO_WIDTH : integer := 6; PRIOR_INFO_WIDTH: integer := 8; BRANCH_MATRIC_WIDTH: integer := 9; STATE_MATRIC_WIDTH: integer := 12 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; ys : in vl_logic_vector; yp : in vl_logic_vector; la : in vl_logic_vector; beta_source_val : in vl_logic; new_beta_cal : in vl_logic; clr_beta : in vl_logic; beta : out vl_logic_vector; gamma : out vl_logic_vector; ys_beta_out : out vl_logic_vector; la_beta_out : out vl_logic_vector; beta_sink_val : out vl_logic );end beta_cal;
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