_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity ctc_tx_fsm is
    generic(
        IDLE            : integer := 1;
        RD_FIFO1        : integer := 2;
        WT1             : integer := 4;
        WR_FIFO1        : integer := 8;
        RD_FIFO2        : integer := 16;
        WT2             : integer := 32;
        WR_FIFO2        : integer := 64;
        RD_FIFO3        : integer := 128;
        WT3             : integer := 256;
        WR_FIFO3        : integer := 512
    );
    port(
        ctc_fifo1_rddat : in     vl_logic_vector(31 downto 0);
        ctc_fifo1_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo1_empty : in     vl_logic;
        ctc_fifo1_rdreq : out    vl_logic;
        ctc_fifo2_rddat : in     vl_logic_vector(31 downto 0);
        ctc_fifo2_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo2_empty : in     vl_logic;
        ctc_fifo2_rdreq : out    vl_logic;
        ctc_fifo3_rddat : in     vl_logic_vector(31 downto 0);
        ctc_fifo3_usedw : in     vl_logic_vector(8 downto 0);
        ctc_fifo3_empty : in     vl_logic;
        ctc_fifo3_rdreq : out    vl_logic;
        full_post_ctc_fifo: in     vl_logic;
        empty_post_ctc_fifo: in     vl_logic;
        wrusedword_post_ctc_fifo: in     vl_logic_vector(8 downto 0);
        wr_post_ctc_fifo: out    vl_logic;
        eop_wr_post_ctc_fifo: out    vl_logic;
        dat_wr_post_ctc_fifo: out    vl_logic_vector(31 downto 0);
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic;
        tx_counter1_nc  : out    vl_logic_vector(15 downto 0);
        tx_counter2_nc  : out    vl_logic_vector(15 downto 0);
        tx_counter3_nc  : out    vl_logic_vector(15 downto 0)
    );
end ctc_tx_fsm;