_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity sld_signaltap is
    generic(
        SLD_NODE_CRC_LOWORD: integer := 50132;
        SLD_RAM_BLOCK_TYPE: string  := "AUTO";
        SLD_ADVANCED_TRIGGER_ENTITY: string  := "basic";
        SLD_ADVANCED_TRIGGER_1: string  := "NONE";
        SLD_MEM_ADDRESS_BITS: integer := 7;
        SLD_TRIGGER_BITS: integer := 8;
        SLD_ADVANCED_TRIGGER_2: string  := "NONE";
        SLD_TRIGGER_LEVEL: integer := 1;
        SLD_ADVANCED_TRIGGER_3: string  := "NONE";
        SLD_ADVANCED_TRIGGER_4: string  := "NONE";
        SLD_ADVANCED_TRIGGER_5: string  := "NONE";
        SLD_ADVANCED_TRIGGER_6: string  := "NONE";
        SLD_ENABLE_ADVANCED_TRIGGER: integer := 0;
        SLD_NODE_CRC_HIWORD: integer := 41394;
        SLD_ADVANCED_TRIGGER_7: string  := "NONE";
        SLD_TRIGGER_LEVEL_PIPELINE: integer := 1;
        SLD_ADVANCED_TRIGGER_8: string  := "NONE";
        SLD_ADVANCED_TRIGGER_9: string  := "NONE";
        SLD_INCREMENTAL_ROUTING: integer := 0;
        SLD_ADVANCED_TRIGGER_10: string  := "NONE";
        SLD_TRIGGER_IN_ENABLED: integer := 1;
        SLD_NODE_CRC_BITS: integer := 32;
        SLD_SAMPLE_DEPTH: integer := 128;
        SLD_DATA_BIT_CNTR_BITS: integer := 4;
        SLD_DATA_BITS   : integer := 8;
        ELA_STATUS_BITS : integer := 3;
        MAX_NUMBER_OF_BITS_FOR_TRIGGERS: integer := 4
    );
    port(
        ir_in           : in     vl_logic_vector;
        update          : in     vl_logic;
        acq_trigger_out : out    vl_logic_vector;
        acq_data_in     : in     vl_logic_vector;
        jtag_state_udr  : in     vl_logic;
        shift           : in     vl_logic;
        trigger_in      : in     vl_logic;
        trigger_out     : out    vl_logic;
        jtag_state_cdr  : in     vl_logic;
        acq_trigger_in  : in     vl_logic_vector;
        usr1            : in     vl_logic;
        clrn            : in     vl_logic;
        jtag_state_uir  : in     vl_logic;
        rti             : in     vl_logic;
        jtag_state_e1dr : in     vl_logic;
        ena             : in     vl_logic;
        tdi             : in     vl_logic;
        crc             : in     vl_logic_vector;
        irq             : out    vl_logic;
        tdo             : out    vl_logic;
        jtag_state_sdr  : in     vl_logic
    );
end sld_signaltap;