_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity pre_ctc_dat_fifo is
    port(
        aclr            : in     vl_logic;
        data            : in     vl_logic_vector(31 downto 0);
        rdclk           : in     vl_logic;
        rdreq           : in     vl_logic;
        wrclk           : in     vl_logic;
        wrreq           : in     vl_logic;
        q               : out    vl_logic_vector(31 downto 0);
        rdempty         : out    vl_logic;
        rdusedw         : out    vl_logic_vector(12 downto 0);
        wrfull          : out    vl_logic;
        wrusedw         : out    vl_logic_vector(12 downto 0)
    );
end pre_ctc_dat_fifo;