_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity alpha_ram is
    port(
        clock           : in     vl_logic;
        data            : in     vl_logic_vector(95 downto 0);
        rdaddress       : in     vl_logic_vector(6 downto 0);
        rden            : in     vl_logic;
        wraddress       : in     vl_logic_vector(6 downto 0);
        wren            : in     vl_logic;
        q               : out    vl_logic_vector(95 downto 0)
    );
end alpha_ram;