_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity ctc_mctrl is
    generic(
        WIN_SIZE        : integer := 32;
        IDLE            : integer := 1;
        \WAIT\          : integer := 2;
        RD              : integer := 4;
        EOP             : integer := 8;
        DEC_ED          : integer := 16;
        DEC_AD          : integer := 32
    );
    port(
        core_gnt        : in     vl_logic;
        wr_over         : in     vl_logic;
        rx2ctrl_length  : in     vl_logic_vector(15 downto 0);
        rx2ctrl_type    : in     vl_logic_vector(2 downto 0);
        rx2ctrl_frame_end_flag: in     vl_logic_vector(2 downto 0);
        rx2ctrl_inst    : in     vl_logic_vector(1 downto 0);
        rx2ctrl_code_rate: in     vl_logic_vector(2 downto 0);
        rx2ctrl_modu_type: in     vl_logic_vector(1 downto 0);
        rx2ctrl_bnum    : in     vl_logic_vector(15 downto 0);
        rx2ctrl_fnum    : in     vl_logic_vector(7 downto 0);
        rx2ctrl_miter   : in     vl_logic_vector(3 downto 0);
        rx2ctrl_segId   : in     vl_logic_vector(3 downto 0);
        dec_finish      : out    vl_logic;
        core_req        : out    vl_logic;
        dpram1_rddat    : in     vl_logic_vector(11 downto 0);
        dpram1_rdadr    : out    vl_logic_vector(11 downto 0);
        dpram1_rd       : out    vl_logic;
        dpram2_rddat    : in     vl_logic_vector(23 downto 0);
        dpram2_rdadr    : out    vl_logic_vector(11 downto 0);
        dpram2_rd       : out    vl_logic;
        le              : in     vl_logic_vector(23 downto 0);
        sop_sink        : in     vl_logic;
        eop_sink        : in     vl_logic;
        val_sink        : in     vl_logic;
        la              : out    vl_logic_vector(23 downto 0);
        ys              : out    vl_logic_vector(11 downto 0);
        yp              : out    vl_logic_vector(11 downto 0);
        sop_source      : out    vl_logic;
        eop_source      : out    vl_logic;
        val_source      : out    vl_logic;
        dat_addr        : in     vl_logic_vector(11 downto 0);
        llrde_addr      : in     vl_logic_vector(11 downto 0);
        mctrl2dat_en    : out    vl_logic;
        mctrl2dat_addr  : out    vl_logic_vector(11 downto 0);
        mctrl2dat_rd    : out    vl_logic;
        mctrl2llrde_addr: out    vl_logic_vector(11 downto 0);
        mctrl2llrde_rd  : out    vl_logic;
        dec_end         : in     vl_logic;
        dec_no          : out    vl_logic_vector(3 downto 0);
        ctrl2resm_length: out    vl_logic_vector(15 downto 0);
        ctrl2resm_type  : out    vl_logic_vector(2 downto 0);
        ctrl2resm_frame_end_flag: out    vl_logic_vector(2 downto 0);
        ctrl2resm_inst  : out    vl_logic_vector(1 downto 0);
        ctrl2resm_code_rate: out    vl_logic_vector(2 downto 0);
        ctrl2resm_modu_type: out    vl_logic_vector(1 downto 0);
        ctrl2resm_bnum  : out    vl_logic_vector(15 downto 0);
        ctrl2resm_fnum  : out    vl_logic_vector(7 downto 0);
        ctrl2resm_miter : out    vl_logic_vector(3 downto 0);
        ctrl2resm_segId : out    vl_logic_vector(3 downto 0);
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic
    );
end ctc_mctrl;