_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity stratixii_mac_pin_map is
    generic(
        operation_mode  : string  := "output_only";
        \type\          : string  := "map"
    );
    port(
        datain          : in     vl_logic_vector(143 downto 0);
        addnsub         : in     vl_logic;
        operation       : in     vl_logic_vector(3 downto 0);
        dataout         : out    vl_logic_vector(143 downto 0)
    );
end stratixii_mac_pin_map;