_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 28 行

library verilog;
use verilog.vl_types.all;
entity viterbi is
    port(
        bestadd         : out    vl_logic_vector(5 downto 0);
        bestmet         : out    vl_logic_vector(12 downto 0);
        clk             : in     vl_logic;
        decbit          : out    vl_logic;
        eras_sym        : in     vl_logic_vector(1 downto 0);
        normalizations  : out    vl_logic_vector(7 downto 0);
        reset           : in     vl_logic;
        rr              : in     vl_logic_vector(15 downto 0);
        sink_dav_master : in     vl_logic;
        sink_ena_master : out    vl_logic;
        sink_eop        : in     vl_logic;
        sink_sop        : in     vl_logic;
        sink_val        : in     vl_logic;
        source_dav_slave: out    vl_logic;
        source_ena_slave: in     vl_logic;
        source_eop      : out    vl_logic;
        source_sop      : out    vl_logic;
        source_val      : out    vl_logic;
        tb_length       : in     vl_logic_vector(6 downto 0);
        tb_type         : in     vl_logic;
        tr_init_state   : in     vl_logic_vector(5 downto 0)
    );
end viterbi;