_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 35 行

library verilog;
use verilog.vl_types.all;
entity output_packer is
    generic(
        WIN_SIZE        : integer := 32;
        OUT_FIFO_DEPTH_WIDTH: integer := 9
    );
    port(
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic;
        d               : in     vl_logic_vector(1 downto 0);
        sop_sink        : in     vl_logic;
        eop_sink        : in     vl_logic;
        val_sink        : in     vl_logic;
        packet_type     : in     vl_logic_vector(2 downto 0);
        packet_frame_end_flag: in     vl_logic_vector(2 downto 0);
        instance_num    : in     vl_logic_vector(1 downto 0);
        packet_length   : in     vl_logic_vector(15 downto 0);
        code_rate       : in     vl_logic_vector(2 downto 0);
        modulate_type   : in     vl_logic_vector(1 downto 0);
        burst_id        : in     vl_logic_vector(15 downto 0);
        fec_id          : in     vl_logic_vector(7 downto 0);
        real_iter_no    : in     vl_logic_vector(4 downto 0);
        segId           : in     vl_logic_vector(3 downto 0);
        iter_stop       : in     vl_logic;
        ready           : out    vl_logic;
        rd_int_ram      : out    vl_logic;
        dat_rd_int_ram  : in     vl_logic_vector(11 downto 0);
        adr_rd_int_ram  : out    vl_logic_vector(11 downto 0);
        fifo_usedword   : in     vl_logic_vector;
        dat_wr_fifo     : out    vl_logic_vector(31 downto 0);
        wr_fifo         : out    vl_logic
    );
end output_packer;