📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity sliding_win_fsm is generic( WIN_SIZE : integer := 32 ); port( clk_sys : in vl_logic; rst_b : in vl_logic; sop_source : in vl_logic; eop_source : in vl_logic; val_source : in vl_logic; alpha_sink_val : in vl_logic; beta_sink_val0 : in vl_logic; beta_sink_val1 : in vl_logic; packet_length : in vl_logic_vector(15 downto 0); clr_cal_buf : out vl_logic; beta_sel : out vl_logic_vector(1 downto 0); new_beta_cal0 : out vl_logic; new_beta_cal1 : out vl_logic; rd_cir_buf_cell0: out vl_logic; rd_cir_buf_cell1: out vl_logic; rd_cir_buf_cell2: out vl_logic; wr_alpha_buf : out vl_logic; rd_alpha_buf : out vl_logic; sop_sink : out vl_logic; eop_sink : out vl_logic );end sliding_win_fsm;
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