_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity mod_max4_a_6 is
    port(
        r5_11           : out    vl_logic;
        r0_11           : out    vl_logic;
        r3_11           : out    vl_logic;
        r1_11           : out    vl_logic;
        r4_11           : out    vl_logic;
        alpha62_11      : in     vl_logic;
        alpha62_10      : in     vl_logic;
        alpha62_9       : in     vl_logic;
        alpha62_8       : in     vl_logic;
        alpha62_7       : in     vl_logic;
        alpha62_6       : in     vl_logic;
        alpha62_5       : in     vl_logic;
        alpha62_4       : in     vl_logic;
        alpha62_3       : in     vl_logic;
        alpha62_2       : in     vl_logic;
        alpha62_1       : in     vl_logic;
        alpha62_0       : in     vl_logic;
        alpha63_11      : in     vl_logic;
        alpha63_10      : in     vl_logic;
        alpha63_9       : in     vl_logic;
        alpha63_8       : in     vl_logic;
        alpha63_7       : in     vl_logic;
        alpha63_6       : in     vl_logic;
        alpha63_5       : in     vl_logic;
        alpha63_4       : in     vl_logic;
        alpha63_3       : in     vl_logic;
        alpha63_2       : in     vl_logic;
        alpha63_1       : in     vl_logic;
        alpha63_0       : in     vl_logic;
        alpha61_11      : in     vl_logic;
        alpha61_10      : in     vl_logic;
        alpha61_9       : in     vl_logic;
        alpha61_8       : in     vl_logic;
        alpha61_7       : in     vl_logic;
        alpha61_6       : in     vl_logic;
        alpha61_5       : in     vl_logic;
        alpha61_4       : in     vl_logic;
        alpha61_3       : in     vl_logic;
        alpha61_2       : in     vl_logic;
        alpha61_1       : in     vl_logic;
        alpha61_0       : in     vl_logic;
        alpha60_11      : in     vl_logic;
        alpha60_10      : in     vl_logic;
        alpha60_9       : in     vl_logic;
        alpha60_8       : in     vl_logic;
        alpha60_7       : in     vl_logic;
        alpha60_6       : in     vl_logic;
        alpha60_5       : in     vl_logic;
        alpha60_4       : in     vl_logic;
        alpha60_3       : in     vl_logic;
        alpha60_2       : in     vl_logic;
        alpha60_1       : in     vl_logic;
        alpha60_0       : in     vl_logic;
        alpha_t6_11     : out    vl_logic;
        alpha_t6_10     : out    vl_logic;
        alpha_t6_9      : out    vl_logic;
        alpha_t6_8      : out    vl_logic;
        alpha_t6_7      : out    vl_logic;
        alpha_t6_6      : out    vl_logic;
        alpha_t6_5      : out    vl_logic;
        alpha_t6_4      : out    vl_logic;
        alpha_t6_3      : out    vl_logic;
        alpha_t6_2      : out    vl_logic;
        alpha_t6_1      : out    vl_logic;
        alpha_t6_0      : out    vl_logic;
        G_127_combout   : in     vl_logic
    );
end mod_max4_a_6;