_primary.vhd

上传的是WIMAX系统中

library verilog;
use verilog.vl_types.all;
entity tbcc_decoder_core is
    generic(
        INIT_WIN_SIZE   : integer := 110;
        BACK_WIN_SIZE   : integer := 110;
        IN_READY        : integer := 1;
        IN_ENA_VITERBI  : integer := 2;
        IN_INIT         : integer := 4;
        IN_DECODING     : integer := 8;
        IN_WAITING      : integer := 16;
        IN_IDLE         : integer := 32;
        OUT0_READY      : integer := 1;
        OUT0_INIT_WIN   : integer := 2;
        OUT0_VALID_DAT_P0: integer := 4;
        OUT0_VALID_DAT_P1: integer := 8;
        OUT0_BACK_WIN   : integer := 16;
        OUT1_READY      : integer := 1;
        OUT1_WAIT_ENA   : integer := 2;
        OUT1_VALID_DAT_P0: integer := 4;
        OUT1_VALID_DAT_P1: integer := 8
    );
    port(
        dec_source_ena  : in     vl_logic;
        buffer_status_in: in     vl_logic_vector(1 downto 0);
        dat_rd_ram_a    : in     vl_logic_vector(15 downto 0);
        dat_rd_ram_b    : in     vl_logic_vector(15 downto 0);
        para_reg_a      : in     vl_logic_vector(50 downto 0);
        para_reg_b      : in     vl_logic_vector(50 downto 0);
        dec_source_data : out    vl_logic_vector(31 downto 0);
        dec_source_dav  : out    vl_logic;
        dec_source_sop  : out    vl_logic;
        dec_source_eop  : out    vl_logic;
        dec_source_val  : out    vl_logic;
        buffer_status_clr: out    vl_logic_vector(1 downto 0);
        adr_rd_ram      : out    vl_logic_vector(8 downto 0);
        rd_ram_a        : out    vl_logic;
        rd_ram_b        : out    vl_logic;
        para_out        : out    vl_logic_vector(50 downto 0);
        en_ping_tx      : out    vl_logic;
        en_pong_tx      : out    vl_logic;
        clk_sys         : in     vl_logic;
        rst_b           : in     vl_logic
    );
end tbcc_decoder_core;