_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity stratixii_mac_bit_register is
    generic(
        data_width      : integer := 1;
        power_up        : integer := 0
    );
    port(
        data            : in     vl_logic;
        clk             : in     vl_logic;
        aclr            : in     vl_logic;
        if_aclr         : in     vl_logic;
        ena             : in     vl_logic;
        async           : in     vl_logic;
        dataout         : out    vl_logic
    );
end stratixii_mac_bit_register;