_primary.vhd

来自「上传的是WIMAX系统中」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity ctc_decoder is
    port(
        sys_clk         : in     vl_logic;
        reset_b         : in     vl_logic;
        empty_pre_ctc_fifo: in     vl_logic;
        usedw_pre_ctc_fifo: in     vl_logic_vector(12 downto 0);
        rd_pre_ctc_fifo : out    vl_logic;
        eop_rd_pre_ctc_fifo: in     vl_logic;
        dat_rd_pre_ctc_fifo: in     vl_logic_vector(31 downto 0);
        full_post_ctc_fifo: in     vl_logic;
        empty_post_ctc_fifo: in     vl_logic;
        wr_post_ctc_fifo: out    vl_logic;
        eop_wr_post_ctc_fifo: out    vl_logic;
        dat_wr_post_ctc_fifo: out    vl_logic_vector(31 downto 0);
        wrusedword_post_ctc_fifo: in     vl_logic_vector(8 downto 0)
    );
end ctc_decoder;