📄 _primary.vhd
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library verilog;use verilog.vl_types.all;entity ctc_decoder is port( sys_clk : in vl_logic; reset_b : in vl_logic; empty_pre_ctc_fifo: in vl_logic; usedw_pre_ctc_fifo: in vl_logic_vector(12 downto 0); rd_pre_ctc_fifo : out vl_logic; eop_rd_pre_ctc_fifo: in vl_logic; dat_rd_pre_ctc_fifo: in vl_logic_vector(31 downto 0); full_post_ctc_fifo: in vl_logic; empty_post_ctc_fifo: in vl_logic; wr_post_ctc_fifo: out vl_logic; eop_wr_post_ctc_fifo: out vl_logic; dat_wr_post_ctc_fifo: out vl_logic_vector(31 downto 0); wrusedword_post_ctc_fifo: in vl_logic_vector(8 downto 0) );end ctc_decoder;
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